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init: DLD154V4B 单路车检器项目

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wangfq
2026-06-22 18:20:37 +08:00
commit 7b95eb1183
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1174
utilities/at32f421_freertos_demo/src/TaskLoop.c Normal file
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utilities/at32f421_freertos_demo/src/at32f421_clock.c Normal file
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/**
**************************************************************************
* @file at32f421_clock.c
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_clock.h"
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* system clock (sclk) = hext * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 120000000
* - ahbdiv = 1
* - ahbclk = 120000000
* - apb2div = 1
* - apb2clk = 120000000
* - apb1div = 1
* - apb1clk = 120000000
* - pll_mult = 15
* - flash_wtcyc = 3 cycle
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* config flash psr register */
flash_psr_set(FLASH_WAIT_CYCLE_3);
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_10);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 120 MHz */
crm_apb2_div_set(CRM_APB2_DIV_1);
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 120 MHz */
crm_apb1_div_set(CRM_APB1_DIV_1);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}

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utilities/at32f421_freertos_demo/src/at32f421_int.c Normal file
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/**
**************************************************************************
* @file at32f421_int.c
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_int.h"
/** @addtogroup FreeRTOS_demo
* @{
*/
/**
* @brief this function handles nmi exception.
* @param none
* @retval none
*/
void NMI_Handler(void)
{
}
/**
* @brief this function handles hard fault exception.
* @param none
* @retval none
*/
void HardFault_Handler(void)
{
/* go to infinite loop when hard fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles memory manage exception.
* @param none
* @retval none
*/
void MemManage_Handler(void)
{
/* go to infinite loop when memory manage exception occurs */
while(1)
{
}
}
/**
* @brief this function handles bus fault exception.
* @param none
* @retval none
*/
void BusFault_Handler(void)
{
/* go to infinite loop when bus fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles usage fault exception.
* @param none
* @retval none
*/
void UsageFault_Handler(void)
{
/* go to infinite loop when usage fault exception occurs */
while(1)
{
}
}
/**
* @brief this function handles svcall exception.
* @param none
* @retval none
*/
//void SVC_Handler(void)
//{
//}
/**
* @brief this function handles debug monitor exception.
* @param none
* @retval none
*/
void DebugMon_Handler(void)
{
}
/**
* @brief this function handles pendsv_handler exception.
* @param none
* @retval none
*/
//void PendSV_Handler(void)
//{
//}
/**
* @brief this function handles systick handler.
* @param none
* @retval none
*/
//void SysTick_Handler(void)
//{
//}
/**
* @}
*/
/**
* @}
*/

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utilities/at32f421_freertos_demo/src/include_port.c Normal file
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/**
**************************************************************************
* @file include_port.c
* @brief include_port program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup FreeRTOS_demo
* @{
*/
/* support ac5 and ac6 compiler */
#if (__ARMCC_VERSION > 6000000)
#include "..\..\..\middlewares\freertos\source\portable\GCC\ARM_CM3\port.c"
#else
#include "..\..\..\middlewares\freertos\source\portable\rvds\ARM_CM3\port.c"
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file main.c
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_board.h"
#include "at32f421_clock.h"
#include "FreeRTOS.h"
#include "task.h"
#include "cmcng.h"
#include "TaskLoop.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup FreeRTOS_demo
* @{
*/
crm_clocks_freq_type g_crm_clocks_freq_struct = {0};
tmr_input_config_type g_tmr_input_config_struct;
__IO uint32_t sys_counter = 0;
uint8_t g_input_div = 1;
TaskHandle_t loop_task_handler;
tmr_output_config_type tmr_oc_init_structure;
/*
pb1 output pwm waveform, use Tmr14.
tmr3 channel1 duty cycle = (tmr3_c1dt/ tmr3_pr)* 100 = 50%
tmr3 channel2 duty cycle = (tmr3_c2dt/ tmr3_pr)* 100 = 37.5%
tmr3 channel3 duty cycle = (tmr3_c3dt/ tmr3_pr)* 100 = 25%
tmr3 channel4 duty cycle = (tmr3_c4dt/ tmr3_pr)* 100 = 12.5%
*/
uint16_t c1dt_val = 333;
//uint16_t c2dt_val = 249;
//uint16_t c3dt_val = 166;
//uint16_t c4dt_val = 83;
uint16_t prescaler_value = 0;
__IO uint16_t pulse=0;//55; //脉冲宽度
uint8_t g_pulse_counter = 0;
uint8_t g_flag_pulse = 1;
/* Basic timr6 */
void Timr6_Init(void)
{
crm_periph_clock_enable(CRM_TMR6_PERIPH_CLOCK, TRUE);
//TODO: 定时的计算方法
// tmr_base_init(TMR6, 9999, (g_crm_clocks_freq_struct.ahb_freq / 10000) - 1); // 1s
tmr_base_init(TMR6, 999, (g_crm_clocks_freq_struct.ahb_freq / 1000000) - 1); // 1ms
tmr_cnt_dir_set(TMR6, TMR_COUNT_UP);
tmr_interrupt_enable(TMR6, TMR_OVF_INT, TRUE);
nvic_irq_enable(TMR6_GLOBAL_IRQn, 0, 0);
tmr_counter_enable(TMR6, TRUE);
// crm_periph_clock_enable(CRM_TMR14_PERIPH_CLOCK, TRUE);
//
// //TODO: 定时的计算方法
//// tmr_base_init(TMR6, 9999, (g_crm_clocks_freq_struct.ahb_freq / 10000) - 1); // 1s
// tmr_base_init(TMR14, (5000-1), (g_crm_clocks_freq_struct.ahb_freq / 1000000) - 1); // 5ms
//// tmr_base_init(TMR14, 9999, (g_crm_clocks_freq_struct.ahb_freq / 1000000) - 1); // 10ms
//
//
// tmr_cnt_dir_set(TMR14, TMR_COUNT_UP);
//
// tmr_interrupt_enable(TMR14, TMR_OVF_INT, TRUE);
//
// nvic_irq_enable(TMR14_GLOBAL_IRQn, 0, 0);
//
// tmr_counter_enable(TMR14, TRUE);
crm_periph_clock_enable(CRM_TMR15_PERIPH_CLOCK, TRUE);
//TODO: 定时的计算方法
// tmr_base_init(TMR6, 9999, (g_crm_clocks_freq_struct.ahb_freq / 10000) - 1); // 1s
tmr_base_init(TMR15, (5000-1), (g_crm_clocks_freq_struct.ahb_freq / 1000000) - 1); // 5ms
// tmr_base_init(TMR14, 9999, (g_crm_clocks_freq_struct.ahb_freq / 1000000) - 1); // 10ms
tmr_cnt_dir_set(TMR15, TMR_COUNT_UP);
tmr_interrupt_enable(TMR15, TMR_OVF_INT, TRUE);
nvic_irq_enable(TMR15_GLOBAL_IRQn, 0, 0);
tmr_counter_enable(TMR15, TRUE);
gpio_init_type gpio_init_struct;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_1;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE1, GPIO_MUX_0);
crm_periph_clock_enable(CRM_TMR14_PERIPH_CLOCK, TRUE);
/* compute the prescaler value */
prescaler_value = (uint16_t)(system_core_clock / 24000000) - 1;
tmr_base_init(TMR14, 665, prescaler_value);
tmr_cnt_dir_set(TMR14, TMR_COUNT_UP);
tmr_clock_source_div_set(TMR14, TMR_CLOCK_DIV1);
tmr_output_default_para_init(&tmr_oc_init_structure);
tmr_oc_init_structure.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
tmr_oc_init_structure.oc_idle_state = FALSE;
tmr_oc_init_structure.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
tmr_oc_init_structure.oc_output_state = TRUE;
c1dt_val = 670;
tmr_output_channel_config(TMR14, TMR_SELECT_CHANNEL_1, &tmr_oc_init_structure);
tmr_channel_value_set(TMR14, TMR_SELECT_CHANNEL_1, c1dt_val);
tmr_output_channel_buffer_enable(TMR14, TMR_SELECT_CHANNEL_1, TRUE);
tmr_period_buffer_enable(TMR14, TRUE);
/* tmr enable counter */
tmr_counter_enable(TMR14, TRUE);
}
uint8_t g_cnt_pwm_red_low_timeout = 0;
void poll_red_pwm(void)
{
g_pulse_counter++;
if(g_pulse_counter >= 12){
g_pulse_counter = 0;
if(g_flag_pulse){
if(pulse < 500){
pulse += 100;
}
else{
pulse += 20;
}
if(pulse >= 670)
{
if(g_cnt_pwm_red_low_timeout < 3){
pulse = 665;
g_cnt_pwm_red_low_timeout++;
}
else{
g_flag_pulse = 0;
g_cnt_pwm_red_low_timeout = 0;
pulse = 660;
}
}
}
else{
if(pulse <= 600)
{
pulse -= 100;
}
else{
pulse -= 20;
}
if(pulse == 0){
g_flag_pulse = 1;
}
}
tmr_channel_value_set(TMR14, TMR_SELECT_CHANNEL_1, pulse);
}
}
/**
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
system_clock_config();
/* get system clock */
crm_clocks_freq_get(&g_crm_clocks_freq_struct);
at32_board_init();
/* init usart1 */
//2250000
// 115200
#ifdef DEBUG
uart_print_init(230400); //115200
PRINT("sys_clock:%d, ahb_freq:%d, sclk_freq:%d\n", system_core_clock, g_crm_clocks_freq_struct.ahb_freq, g_crm_clocks_freq_struct.sclk_freq);
#endif
loop_timer_io_init();
Timr6_Init();
/* enter critical */
taskENTER_CRITICAL();
/* create loop task */
if(xTaskCreate((TaskFunction_t )loop_task_function,
(const char* )"Loop_task",
(uint16_t )512,
(void* )NULL,
(UBaseType_t )2,
(TaskHandle_t* )&loop_task_handler) != pdPASS)
{
PRINT("loop task could not be created as there was insufficient heap memory remaining.\r\n");
}
else
{
PRINT("loop task was created successfully.\r\n");
}
/* exit critical */
taskEXIT_CRITICAL();
/* start scheduler */
vTaskStartScheduler();
}
uint8_t g_flag_output = 0;
uint8_t g_flag_output2 = 0;
// 1ms interval
void TMR6_GLOBAL_IRQHandler(void)
{
static uint16_t _cnt_5ms = 0;
static uint32_t _cnt = 0;
if(tmr_interrupt_flag_get(TMR6, TMR_OVF_FLAG) != RESET)
{
#ifdef DEBUG
_cnt++;
if(_cnt >= 2000){
g_flag_output = 1;
_cnt = 0;
}
#endif
tmr_flag_clear(TMR6, TMR_OVF_FLAG);
}
}
/**
* @}
*/
/**
* @}
*/