Files
DLD154V4B/utilities/at32f421_freertos_demo/inc/cmcng.h
T
wangfq e1b5542296 feat(V4B): V4.36.18 — 频率窗下界 20→18kHz
COIL_F_OK_MIN_KHZ 18: 合理窗 18~125kHz (@43nF ≈ L47µH~1.15mH) 放行更大电感
test 边界 17偏大/18正常 全绿; 镜像同步
顺带修正 spec 参数表历史滞后: MAX 115→125, COIL_CAL_C_NF 68→43
语法0 error; spec V2.34 / manual / devlog V2.53
2026-09-04 17:35:41 +08:00

74 lines
1.8 KiB
C

/**
**************************************************************************
* @file cmcng.h
* @version v1.0
* @date 2025-09-08
* @brief 一些配置
**************************************************************************
* Copyright notice & Disclaimer
* * Create 2025-09-08 by wangfq
* *
**************************************************************************
*/
#ifndef __CMCNG_H__
#define __CMCNG_H__
#define PRODUCT_MODEL "DLD154"
#define FIRMWARE_VER "4.36.18" // 主.子.修订 (2026-09-03 起: 小改动只增 REV; MAIN/SUB 由产品定)
#define HARDWARE_VER "3.00"
#define FIRMWARE_VER_MAIN 4
#define FIRMWARE_VER_SUB 36
#define FIRMWARE_VER_REV 18
#define HARDWARE_VER_MAIN 3
#define HARDWARE_VER_SUB 0
#include <stdio.h>
#include <stdint.h>
#ifdef DEBUG
#define PRINT(X...) printf(X)
#else
#define PRINT(X...)
#endif
typedef struct _LOOP_ACS_INFO
{
uint8_t flag_event;
uint8_t loop_num;
uint8_t freq_level;
uint8_t sensity;
uint8_t relay1_cng;
uint8_t relay1_state;
uint8_t relay2_cng;
uint8_t relay2_state;
uint8_t loop_state;
uint8_t output_mode;
uint8_t dir_mode;
uint8_t delay;
uint8_t car_state;
uint8_t direction;
uint8_t flag_loop_safe;
uint32_t loop_safe_counter;
uint8_t condition;
uint32_t frequent;
uint32_t loop_capvd;
int16_t variation;
uint32_t event_counter;
uint32_t report_counter;
} Loop_ACS_Info;
extern Loop_ACS_Info g_loop_acs_info;
extern uint8_t g_flag_output;
extern uint8_t g_flag_output2;
extern uint8_t g_input_div;
#endif