diff --git a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/offlog.h b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/offlog.h
index 26e8de7..e70050c 100644
--- a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/offlog.h
+++ b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/offlog.h
@@ -98,6 +98,11 @@ enum {
     OFFLOG_EVT_LOG_CLEAR    = 0x70,  /* 日志清除 (审计)                                     */
 };
 
+/* 复位原因寄存器 (CH32V20x RCC 基址 0x40021000, RSTSCKR 偏移 0x24,
+   STM32F1 兼容布局; 若实际硬件布局不同, 读出的原因位会异常, 待板上验证) */
+#define OFFLOG_RCC_BASE         0x40021000UL
+#define OFFLOG_RCC_RSTSCKR      (*(volatile uint32_t *)(OFFLOG_RCC_BASE + 0x24UL))
+
 /* 复位原因位 (RCC_RSTSCKR, STM32F1/CH32V20x 兼容布局, 待板上验证) */
 #define OFFLOG_RST_IWDG      (1UL << 31)  /* 独立看门狗复位 (IWDG 超时 → 主循环卡死!)  */
 #define OFFLOG_RST_WWDG      (1UL << 30)  /* 窗口看门狗复位                            */
diff --git a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/storage.h b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/storage.h
index d0d0bf7..5a169ef 100644
--- a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/storage.h
+++ b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/include/storage.h
@@ -33,6 +33,7 @@ void load_cfg_from_flash(void);
 void SPI_Flash_Read(uint8_t *pBuffer, uint32_t ReadAddr, uint16_t size);
 void SPI_Flash_Write(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
 void SPI_Flash_Write_NoCheck(uint8_t *pBuffer, uint32_t WriteAddr, uint16_t size);
+void SPI_Flash_Erase_Sector(uint32_t Dst_Addr);
 
 void storage_init(void);
 
diff --git a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/offlog.c b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/offlog.c
index 50cb774..ea61454 100644
--- a/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/offlog.c
+++ b/vd960DBN/BLE/OnlyUpdateApp_Peripheral/APP/offlog.c
@@ -31,11 +31,6 @@ static uint16_t _boot_seq;      /* 当前 boot 序号                        */
 static uint32_t _count;         /* 有效记录数 (0..8064)                  */
 static uint8_t  _ready;         /* init 完成标志                         */
 
-/* 复位原因寄存器 (CH32V20x RCC 基址 0x40021000, RSTSCKR 偏移 0x24,
-   STM32F1 兼容布局; 若实际硬件布局不同, 读出的原因位会异常, 待板上验证) */
-#define OFFLOG_RCC_BASE         0x40021000UL
-#define OFFLOG_RCC_RSTSCKR      (*(volatile uint32_t *)(OFFLOG_RCC_BASE + 0x24UL))
-
 /*===========================================================================
  * 基础读写
  *===========================================================================*/