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feat(V4B): V4.35 — 频率窗上限复核 92→108kHz (43nF板口径≈50µH)

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V4.33 的 92k 是 0Ω 实验板(68nF)语境; 产品回到三极管板(43nF)后 92k≈70µH 过严,
40~70µH 正常线圈会误报 → 上限 108k = L≈50µH (保留最小合理线圈)
test_coil_range 边界 108/109 全绿; 语法 0 error
文档: devlog V2.33 / spec V2.14 / manual V2.11
This commit is contained in:
wangfq
2026-09-03 17:13:00 +08:00
parent be91c584ee
commit f6e2a82935
6 changed files with 47 additions and 14 deletions
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utilities/at32f421_freertos_demo/inc/cmcng.h
+2 -2
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@@ -14,10 +14,10 @@
#define __CMCNG_H__
#define PRODUCT_MODEL "DLD154"
#define FIRMWARE_VER "4.34"
#define FIRMWARE_VER "4.35"
#define HARDWARE_VER "3.00"
#define FIRMWARE_VER_MAIN 4
#define FIRMWARE_VER_SUB 34
#define FIRMWARE_VER_SUB 35
#define HARDWARE_VER_MAIN 3
#define HARDWARE_VER_SUB 0