refactor(vd960Loop): 算法回退到 DLD154V4B，四通道适配

- 用 DLD154V4B vd1_task/per_channel 替换 vds_task 复杂算法
- 移除 FUNCTION_B/二次判断/快速变化/多重确认等增强特性
- 保留平坦性离开算法 (CN200910309382)，每通道独立状态
- 灵敏度表改为 DLD154V4B 4级: {216,108,36,10} / {108,72,18,9}
- 清理废弃类型: FltHistoryManager, Loop_ACS_Info, StageRangeConfig 等
- 首次添加 vd960DBN 完整源码

vd960DBN/SRC/Peripheral/inc/ch32v20x_misc.h

@@ -0,0 +1,72 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v20x_misc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/06/06
+ * Description        : This file contains all the functions prototypes for the
+ *                      miscellaneous firmware library functions.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for 
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32V20x_MISC_H
+#define __CH32V20x_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v20x.h"
+
+/* CSR_INTSYSCR_INEST_definition */
+#define INTSYSCR_INEST_NoEN   0x00   /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
+#define INTSYSCR_INEST_EN     0x01   /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
+
+/* Check the configuration of CSR(0x804) in the startup file(.S)
+ *   interrupt nesting enable(CSR-0x804 bit1 = 1)
+ *     priority - bit[7] - Preemption Priority
+ *                bit[6:5] - Sub priority
+ *                bit[4:0] - Reserve
+ *   interrupt nesting disable(CSR-0x804 bit1 = 0)
+ *     priority - bit[7:5] - Sub priority
+ *                bit[4:0] - Reserve
+ */
+
+#ifndef INTSYSCR_INEST
+#define INTSYSCR_INEST   INTSYSCR_INEST_EN
+#endif
+
+/* NVIC Init Structure definition
+ *   interrupt nesting enable(CSR-0x804 bit1 = 1)
+ *     NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
+ *     NVIC_IRQChannelSubPriority - range from 0 to 3.
+ *
+ *   interrupt nesting disable(CSR-0x804 bit1 = 0)
+ *     NVIC_IRQChannelPreemptionPriority - range is 0.
+ *     NVIC_IRQChannelSubPriority - range from 0 to 7.
+ *
+ */
+typedef struct
+{
+    uint8_t NVIC_IRQChannel;
+    uint8_t NVIC_IRQChannelPreemptionPriority;
+    uint8_t NVIC_IRQChannelSubPriority;
+    FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/* Preemption_Priority_Group */
+#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
+#define NVIC_PriorityGroup_0           ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
+#else
+#define NVIC_PriorityGroup_1           ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
+#endif
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif