refactor(vd960Loop): 算法回退到 DLD154V4B，四通道适配
- 用 DLD154V4B vd1_task/per_channel 替换 vds_task 复杂算法
- 移除 FUNCTION_B/二次判断/快速变化/多重确认等增强特性
- 保留平坦性离开算法 (CN200910309382)，每通道独立状态
- 灵敏度表改为 DLD154V4B 4级: {216,108,36,10} / {108,72,18,9}
- 清理废弃类型: FltHistoryManager, Loop_ACS_Info, StageRangeConfig 等
- 首次添加 vd960DBN 完整源码
This commit is contained in:
wangfq
1210
vd960DBN/SRC/Peripheral/src/ch32v20x_adc.c
Normal file
1210
vd960DBN/SRC/Peripheral/src/ch32v20x_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
244
vd960DBN/SRC/Peripheral/src/ch32v20x_bkp.c
Normal file
244
vd960DBN/SRC/Peripheral/src/ch32v20x_bkp.c
Normal file
@@ -0,0 +1,244 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
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||||
* File Name : ch32v20x_bkp.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2023/01/06
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* Description : This file provides all the BKP firmware functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v20x_bkp.h"
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#include "ch32v20x_rcc.h"
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/* BKP registers bit mask */
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/* OCTLR register bit mask */
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#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
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#define OCTLR_MASK ((uint16_t)0xFC7F)
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/*********************************************************************
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* @fn BKP_DeInit
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*
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* @brief Deinitializes the BKP peripheral registers to their default reset values.
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*
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* @return none
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*/
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void BKP_DeInit(void)
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{
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RCC_BackupResetCmd(ENABLE);
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RCC_BackupResetCmd(DISABLE);
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}
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/*********************************************************************
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* @fn BKP_TamperPinLevelConfig
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*
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* @brief Configures the Tamper Pin active level.
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*
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* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
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* BKP_TamperPinLevel_High - Tamper pin active on high level.
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* BKP_TamperPinLevel_Low - Tamper pin active on low level.
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*
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* @return none
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*/
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void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
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{
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if(BKP_TamperPinLevel)
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{
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BKP->TPCTLR |= (1 << 1);
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}
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else
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{
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BKP->TPCTLR &= ~(1 << 1);
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}
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}
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/*********************************************************************
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* @fn BKP_TamperPinCmd
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*
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* @brief Enables or disables the Tamper Pin activation.
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*
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* @param NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void BKP_TamperPinCmd(FunctionalState NewState)
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{
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if(NewState)
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{
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BKP->TPCTLR |= (1 << 0);
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}
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else
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{
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BKP->TPCTLR &= ~(1 << 0);
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}
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}
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/*********************************************************************
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* @fn BKP_ITConfig
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*
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* @brief Enables or disables the Tamper Pin Interrupt.
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*
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* @param NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void BKP_ITConfig(FunctionalState NewState)
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{
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if(NewState)
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{
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BKP->TPCSR |= (1 << 2);
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}
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else
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{
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BKP->TPCSR &= ~(1 << 2);
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}
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}
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/*********************************************************************
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* @fn BKP_RTCOutputConfig
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*
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* @brief Select the RTC output source to output on the Tamper pin.
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*
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* @param BKP_RTCOutputSource - specifies the RTC output source.
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* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
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* BKP_RTCOutputSource_CalibClock - output the RTC clock with
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* frequency divided by 64 on the Tamper pin.
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* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
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* on the Tamper pin.
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* BKP_RTCOutputSource_Second - output the RTC Second pulse
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* signal on the Tamper pin.
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*
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* @return none
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*/
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void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
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{
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uint16_t tmpreg = 0;
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tmpreg = BKP->OCTLR;
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tmpreg &= OCTLR_MASK;
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tmpreg |= BKP_RTCOutputSource;
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BKP->OCTLR = tmpreg;
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}
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/*********************************************************************
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* @fn BKP_SetRTCCalibrationValue
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*
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* @brief Sets RTC Clock Calibration value.
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*
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* @param CalibrationValue - specifies the RTC Clock Calibration value.
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* This parameter must be a number between 0 and 0x7F.
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*
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* @return none
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*/
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void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
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{
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uint16_t tmpreg = 0;
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tmpreg = BKP->OCTLR;
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tmpreg &= OCTLR_CAL_MASK;
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tmpreg |= CalibrationValue;
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BKP->OCTLR = tmpreg;
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}
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/*********************************************************************
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* @fn BKP_WriteBackupRegister
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*
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* @brief Writes user data to the specified Data Backup Register.
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*
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* @param BKP_DR - specifies the Data Backup Register.
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* Data - data to write.
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*
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* @return none
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*/
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void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
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{
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__IO uint32_t tmp = 0;
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tmp = (uint32_t)BKP_BASE;
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tmp += BKP_DR;
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*(__IO uint32_t *)tmp = Data;
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}
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/*********************************************************************
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* @fn BKP_ReadBackupRegister
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*
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* @brief Reads data from the specified Data Backup Register.
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*
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* @param BKP_DR - specifies the Data Backup Register.
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* This parameter can be BKP_DRx where x=[1, 42].
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*
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* @return none
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*/
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uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
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{
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__IO uint32_t tmp = 0;
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tmp = (uint32_t)BKP_BASE;
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tmp += BKP_DR;
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return (*(__IO uint16_t *)tmp);
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}
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/*********************************************************************
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* @fn BKP_GetFlagStatus
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*
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* @brief Checks whether the Tamper Pin Event flag is set or not.
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*
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* @return FlagStatus - SET or RESET.
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*/
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FlagStatus BKP_GetFlagStatus(void)
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{
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if(BKP->TPCSR & (1 << 8))
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
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/*********************************************************************
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* @fn BKP_ClearFlag
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*
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* @brief Clears Tamper Pin Event pending flag.
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*
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* @return none
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*/
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void BKP_ClearFlag(void)
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{
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BKP->TPCSR |= BKP_CTE;
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}
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/*********************************************************************
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* @fn BKP_GetITStatus
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*
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* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
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*
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* @return ITStatus - SET or RESET.
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*/
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ITStatus BKP_GetITStatus(void)
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{
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if(BKP->TPCSR & (1 << 9))
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{
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return SET;
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}
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else
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{
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return RESET;
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}
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}
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/*********************************************************************
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* @fn BKP_ClearITPendingBit
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*
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* @brief Clears Tamper Pin Interrupt pending bit.
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*
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* @return none
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*/
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void BKP_ClearITPendingBit(void)
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{
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BKP->TPCSR |= BKP_CTI;
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}
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1261
vd960DBN/SRC/Peripheral/src/ch32v20x_can.c
Normal file
1261
vd960DBN/SRC/Peripheral/src/ch32v20x_can.c
Normal file
File diff suppressed because it is too large
Load Diff
99
vd960DBN/SRC/Peripheral/src/ch32v20x_crc.c
Normal file
99
vd960DBN/SRC/Peripheral/src/ch32v20x_crc.c
Normal file
@@ -0,0 +1,99 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v20x_crc.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : This file provides all the CRC firmware functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v20x_crc.h"
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/*********************************************************************
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* @fn CRC_ResetDR
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*
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* @brief Resets the CRC Data register (DR).
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*
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* @return none
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*/
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void CRC_ResetDR(void)
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{
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CRC->CTLR = CRC_CTLR_RESET;
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}
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/*********************************************************************
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* @fn CRC_CalcCRC
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*
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* @brief Computes the 32-bit CRC of a given data word(32-bit).
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*
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* @param Data - data word(32-bit) to compute its CRC.
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*
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* @return 32-bit CRC.
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*/
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uint32_t CRC_CalcCRC(uint32_t Data)
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{
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CRC->DATAR = Data;
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return (CRC->DATAR);
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}
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/*********************************************************************
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* @fn CRC_CalcBlockCRC
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||||
*
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* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
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*
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* @param pBuffer - pointer to the buffer containing the data to be computed.
|
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* BufferLength - length of the buffer to be computed.
|
||||
*
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* @return 32-bit CRC.
|
||||
*/
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uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
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{
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uint32_t index = 0;
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for(index = 0; index < BufferLength; index++){
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CRC->DATAR = pBuffer[index];
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}
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||||
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return (CRC->DATAR);
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}
|
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|
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/*********************************************************************
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||||
* @fn CRC_GetCRC
|
||||
*
|
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* @brief Returns the current CRC value.
|
||||
*
|
||||
* @return 32-bit CRC.
|
||||
*/
|
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uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DATAR);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn CRC_SetIDRegister
|
||||
*
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
*
|
||||
* @param IDValue - 8-bit value to be stored in the ID register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t IDValue)
|
||||
{
|
||||
CRC->IDATAR = IDValue;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn CRC_GetIDRegister
|
||||
*
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||
*
|
||||
* @return 8-bit value of the ID register.
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDATAR);
|
||||
}
|
||||
126
vd960DBN/SRC/Peripheral/src/ch32v20x_dbgmcu.c
Normal file
126
vd960DBN/SRC/Peripheral/src/ch32v20x_dbgmcu.c
Normal file
@@ -0,0 +1,126 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_dbgmcu.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the DBGMCU firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_dbgmcu.h"
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetREVID
|
||||
*
|
||||
* @brief Returns the device revision identifier.
|
||||
*
|
||||
* @return Revision identifier.
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return ((*(uint32_t *)0x1FFFF704) >> 16);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetDEVID
|
||||
*
|
||||
* @brief Returns the device identifier.
|
||||
*
|
||||
* @return Device identifier.
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_DEBUG_CR
|
||||
*
|
||||
* @brief Return the DEBUGE Control Register
|
||||
*
|
||||
* @return DEBUGE Control value
|
||||
*/
|
||||
uint32_t __get_DEBUG_CR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_DEBUG_CR
|
||||
*
|
||||
* @brief Set the DEBUGE Control Register
|
||||
*
|
||||
* @param value - set DEBUGE Control value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_DEBUG_CR(uint32_t value)
|
||||
{
|
||||
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_Config
|
||||
*
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
*
|
||||
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
|
||||
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
|
||||
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
|
||||
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
|
||||
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
__set_DEBUG_CR(DBGMCU_Periph);
|
||||
}
|
||||
else
|
||||
{
|
||||
val = __get_DEBUG_CR();
|
||||
val &= ~(uint32_t)DBGMCU_Periph;
|
||||
__set_DEBUG_CR(val);
|
||||
}
|
||||
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetCHIPID
|
||||
*
|
||||
* @brief Returns the CHIP identifier.
|
||||
*
|
||||
* @return Device identifier.
|
||||
* ChipID List-
|
||||
* CH32V203C8U6-0x203005x0
|
||||
* CH32V203C8T6-0x203105x0
|
||||
* CH32V203K8T6-0x203205x0
|
||||
* CH32V203C6T6-0x203305x0
|
||||
* CH32V203G6U6-0x203605x0
|
||||
* CH32V203G8R6-0x203B05x0
|
||||
* CH32V203F8U6-0x203E05x0
|
||||
* CH32V203F6P6-0x203705x0-0x203905x0
|
||||
* CH32V203F8P6-0x203A05x0
|
||||
* CH32V203RBT6-0x203405xC
|
||||
* CH32V208WBU6-0x208005xC
|
||||
* CH32V208RBT6-0x208105xC
|
||||
* CH32V208CBU6-0x208205xC
|
||||
* CH32V208GBU6-0x208305xC
|
||||
*/
|
||||
uint32_t DBGMCU_GetCHIPID( void )
|
||||
{
|
||||
return( *( uint32_t * )0x1FFFF704 );
|
||||
}
|
||||
432
vd960DBN/SRC/Peripheral/src/ch32v20x_dma.c
Normal file
432
vd960DBN/SRC/Peripheral/src/ch32v20x_dma.c
Normal file
@@ -0,0 +1,432 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_dma.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the DMA firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_dma.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||
#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_DeInit
|
||||
*
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
DMAy_Channelx->CFGR = 0;
|
||||
DMAy_Channelx->CNTR = 0;
|
||||
DMAy_Channelx->PADDR = 0;
|
||||
DMAy_Channelx->MADDR = 0;
|
||||
if(DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel8)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Init
|
||||
*
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMAy_Channelx->CFGR;
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
DMAy_Channelx->CFGR = tmpreg;
|
||||
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
|
||||
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_StructInit
|
||||
*
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
* DMA_IT - specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* DMA_IT_TC - Transfer complete interrupt mask
|
||||
* DMA_IT_HT - Half transfer interrupt mask
|
||||
* DMA_IT_TE - Transfer error interrupt mask
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_SetCurrDataCounter
|
||||
*
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
* DataNumber - The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
DMAy_Channelx->CNTR = DataNumber;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetCurrDataCounter
|
||||
*
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||
*
|
||||
* @return DataNumber - The number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
return ((uint16_t)(DMAy_Channelx->CNTR));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||
|
||||
* @return The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMA1->INTFR;
|
||||
|
||||
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearFlag
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
DMA1->INTFCR = DMAy_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has
|
||||
* occurred or not.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* @return The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMA1->INTFR;
|
||||
|
||||
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
DMA1->INTFCR = DMAy_IT;
|
||||
}
|
||||
182
vd960DBN/SRC/Peripheral/src/ch32v20x_exti.c
Normal file
182
vd960DBN/SRC/Peripheral/src/ch32v20x_exti.c
Normal file
@@ -0,0 +1,182 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_exti.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the EXTI firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_exti.h"
|
||||
|
||||
/* No interrupt selected */
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_DeInit
|
||||
*
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->INTENR = 0x00000000;
|
||||
EXTI->EVENR = 0x00000000;
|
||||
EXTI->RTENR = 0x00000000;
|
||||
EXTI->FTENR = 0x00000000;
|
||||
EXTI->INTFR = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_Init
|
||||
*
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
*
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_StructInit
|
||||
*
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
*
|
||||
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GenerateSWInterrupt
|
||||
*
|
||||
* @brief Generates a Software interrupt.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->SWIEVR |= EXTI_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_ClearFlag
|
||||
*
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->INTFR = EXTI_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
enablestatus = EXTI->INTENR & EXTI_Line;
|
||||
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->INTFR = EXTI_Line;
|
||||
}
|
||||
1232
vd960DBN/SRC/Peripheral/src/ch32v20x_flash.c
Normal file
1232
vd960DBN/SRC/Peripheral/src/ch32v20x_flash.c
Normal file
File diff suppressed because it is too large
Load Diff
999
vd960DBN/SRC/Peripheral/src/ch32v20x_gpio.c
Normal file
999
vd960DBN/SRC/Peripheral/src/ch32v20x_gpio.c
Normal file
@@ -0,0 +1,999 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_gpio.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/06
|
||||
* Description : This file provides all the GPIO firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_gpio.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* MASK */
|
||||
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
uint8_t MCU_Version = 0;
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_DeInit
|
||||
*
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOD)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOE)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_AFIODeInit
|
||||
*
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Init
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
|
||||
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
#if defined (CH32V20x_D6)
|
||||
if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0)
|
||||
{
|
||||
MCU_Version = 1;
|
||||
}
|
||||
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CFGLR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGLR = tmpreg;
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||
{
|
||||
tmpreg = GPIOx->CFGHR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGHR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_StructInit
|
||||
*
|
||||
* @brief Fills each GPIO_InitStruct member with its default
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputDataBit
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputData
|
||||
*
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return The output port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
uint16_t val;
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
val = ( uint16_t )(GPIOx->INDR << 13);
|
||||
}
|
||||
else{
|
||||
val = ( uint16_t )GPIOx->INDR;
|
||||
}
|
||||
|
||||
#else
|
||||
val = ( uint16_t )GPIOx->INDR;
|
||||
#endif
|
||||
|
||||
return ( val );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputDataBit
|
||||
*
|
||||
* @brief Reads the specified output data port bit.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputData
|
||||
*
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return GPIO output port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
uint16_t val;
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
val = ( uint16_t )(GPIOx->OUTDR << 13);
|
||||
}
|
||||
else{
|
||||
val = ( uint16_t )GPIOx->OUTDR;
|
||||
}
|
||||
|
||||
#else
|
||||
val = ( uint16_t )GPIOx->OUTDR;
|
||||
#endif
|
||||
|
||||
return ( val );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_SetBits
|
||||
*
|
||||
* @brief Sets the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
GPIOx->BSHR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ResetBits
|
||||
*
|
||||
* @brief Clears the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_WriteBit
|
||||
*
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* BitVal - specifies the value to be written to the selected bit.
|
||||
* Bit_RESET - to clear the port pin.
|
||||
* Bit_SET - to set the port pin.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
if(BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSHR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Write
|
||||
*
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* PortVal - specifies the value to be written to the port output data register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
|
||||
{
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
PortVal = PortVal >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
GPIOx->OUTDR = PortVal;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinLockConfig
|
||||
*
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
#if defined (CH32V20x_D6)
|
||||
if((GPIOx == GPIOC) && MCU_Version){
|
||||
GPIO_Pin = GPIO_Pin >> 13;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
tmp = GPIOx->LCKR;
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EventOutputConfig
|
||||
*
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
*
|
||||
* @param GPIO_PortSource - selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* GPIO_PinSource - specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = AFIO->ECR;
|
||||
tmpreg &= ECR_PORTPINCONFIG_MASK;
|
||||
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||
tmpreg |= GPIO_PinSource;
|
||||
AFIO->ECR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EventOutputCmd
|
||||
*
|
||||
* @brief Enables or disables the Event Output.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
AFIO->ECR |= (1 << 7);
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->ECR &= ~(1 << 7);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinRemapConfig
|
||||
*
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
*
|
||||
* @param GPIO_Remap - selects the pin to remap.
|
||||
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
|
||||
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
|
||||
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
|
||||
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
|
||||
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
|
||||
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
|
||||
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
|
||||
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
|
||||
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
|
||||
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
|
||||
* GPIO_Remap_ETH - Ethernet remapping
|
||||
* GPIO_Remap_CAN2 - CAN2 remapping
|
||||
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
|
||||
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
|
||||
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
* to TIM2 Internal Trigger 1 for calibration
|
||||
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
|
||||
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
|
||||
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
|
||||
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpreg = AFIO->PCFR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = AFIO->PCFR1;
|
||||
|
||||
if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){
|
||||
tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
/* Clear bit */
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{ /* PCFR2 */
|
||||
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
else /* [31:0] 1bit */
|
||||
{
|
||||
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF ) >> 0x15) * 0x10));
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* PCFR1 */
|
||||
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else /* [31:0] 1bit */
|
||||
{
|
||||
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set bit */
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10));
|
||||
}
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->PCFR2 = tmpreg;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->PCFR1 = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EXTILineConfig
|
||||
*
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
*
|
||||
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* GPIO_PinSource - specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ETH_MediaInterfaceConfig
|
||||
*
|
||||
* @brief Selects the Ethernet media interface.
|
||||
*
|
||||
* @param GPIO_ETH_MediaInterface - specifies the Media Interface mode.
|
||||
* GPIO_ETH_MediaInterface_MII - MII mode
|
||||
* GPIO_ETH_MediaInterface_RMII - RMII mode
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||
{
|
||||
if(GPIO_ETH_MediaInterface)
|
||||
{
|
||||
AFIO->PCFR1 |= (1 << 23);
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->PCFR1 &= ~(1 << 23);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_IPD_Unused
|
||||
*
|
||||
* @brief Configure unused GPIO as input pull-up.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_IPD_Unused(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
uint32_t chip = 0;
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB \
|
||||
| RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD|RCC_APB2Periph_AFIO,ENABLE);
|
||||
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0);
|
||||
switch(chip)
|
||||
{
|
||||
#ifdef CH32V20x_D6
|
||||
case 0x20370500: //CH32V203F6P6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\
|
||||
|GPIO_Pin_3|GPIO_Pin_4\
|
||||
|GPIO_Pin_5|GPIO_Pin_6\
|
||||
|GPIO_Pin_7|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x203A0500: //CH32V203F8P6
|
||||
{
|
||||
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11|GPIO_Pin_12\
|
||||
|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1\
|
||||
|GPIO_Pin_3|GPIO_Pin_4\
|
||||
|GPIO_Pin_5|GPIO_Pin_8\
|
||||
|GPIO_Pin_9|GPIO_Pin_10\
|
||||
|GPIO_Pin_11|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x203E0500: //CH32V203F8U6
|
||||
{
|
||||
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_12|GPIO_Pin_13;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20360500: //CH32V203G6U6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x203B0500: //CH32V203G8R6
|
||||
{
|
||||
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_9;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20320500: //CH32V203K8T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20330500: //CH32V203C6T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20310500: //CH32V203C8T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x20300500: //CH32V203C8U6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
#elif defined(CH32V20x_D8)
|
||||
case 0x2034050C: //CH32V203RBT6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|
||||
|GPIO_Pin_5|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
#elif defined(CH32V20x_D8W)
|
||||
case 0x2083050C: //CH32V208GBU6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_9|GPIO_Pin_10\
|
||||
|GPIO_Pin_11|GPIO_Pin_12\
|
||||
|GPIO_Pin_13|GPIO_Pin_14\
|
||||
|GPIO_Pin_15;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x2082050C: //CH32V208CBU6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x2081050C: //CH32V208RBT6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|
||||
|GPIO_Pin_5|GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
1012
vd960DBN/SRC/Peripheral/src/ch32v20x_i2c.c
Normal file
1012
vd960DBN/SRC/Peripheral/src/ch32v20x_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
123
vd960DBN/SRC/Peripheral/src/ch32v20x_iwdg.c
Normal file
123
vd960DBN/SRC/Peripheral/src/ch32v20x_iwdg.c
Normal file
@@ -0,0 +1,123 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_iwdg.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/12/29
|
||||
* Description : This file provides all the IWDG firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_iwdg.h"
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
|
||||
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_WriteAccessCmd
|
||||
*
|
||||
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
|
||||
*
|
||||
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
|
||||
* IWDG_RLDR registers.
|
||||
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
|
||||
* IWDG_RLDR registers.
|
||||
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
|
||||
* and IWDG_RLDR registers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
IWDG->CTLR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_SetPrescaler
|
||||
*
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
*
|
||||
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
|
||||
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
|
||||
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
|
||||
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
|
||||
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
|
||||
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
|
||||
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
|
||||
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
IWDG->PSCR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_SetReload
|
||||
*
|
||||
* @brief Sets IWDG Reload value.
|
||||
*
|
||||
* @param Reload - specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
IWDG->RLDR = Reload;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_ReloadCounter
|
||||
*
|
||||
* @brief Reloads IWDG counter with value defined in the reload register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->CTLR = CTLR_KEY_Reload;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_Enable
|
||||
*
|
||||
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->CTLR = CTLR_KEY_Enable;
|
||||
while((RCC->RSTSCKR & 0x2)==RESET);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
*
|
||||
* @param IWDG_FLAG - specifies the flag to check.
|
||||
* IWDG_FLAG_PVU - Prescaler Value Update on going.
|
||||
* IWDG_FLAG_RVU - Reload Value Update on going.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
81
vd960DBN/SRC/Peripheral/src/ch32v20x_misc.c
Normal file
81
vd960DBN/SRC/Peripheral/src/ch32v20x_misc.c
Normal file
@@ -0,0 +1,81 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_misc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the miscellaneous firmware functions .
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_misc.h"
|
||||
|
||||
__IO uint32_t NVIC_Priority_Group = 0;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_PriorityGroupConfig
|
||||
*
|
||||
* @brief Configures the priority grouping - pre-emption priority and subpriority.
|
||||
*
|
||||
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
|
||||
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
NVIC_Priority_Group = NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_Init
|
||||
*
|
||||
* @brief Initializes the NVIC peripheral according to the specified parameters in
|
||||
* the NVIC_InitStruct.
|
||||
*
|
||||
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
|
||||
* configuration information for the specified NVIC peripheral.
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||
*
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
|
||||
{
|
||||
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
|
||||
}
|
||||
#else
|
||||
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
|
||||
{
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||
}
|
||||
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
}
|
||||
86
vd960DBN/SRC/Peripheral/src/ch32v20x_opa.c
Normal file
86
vd960DBN/SRC/Peripheral/src/ch32v20x_opa.c
Normal file
@@ -0,0 +1,86 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_opa.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the OPA firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_opa.h"
|
||||
|
||||
#define OPA_MASK ((uint32_t)0x000F)
|
||||
#define OPA_Total_NUM 4
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_DeInit
|
||||
*
|
||||
* @brief Deinitializes the OPA peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_DeInit(void)
|
||||
{
|
||||
OPA->CR = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_Init
|
||||
*
|
||||
* @brief Initializes the OPA peripheral according to the specified
|
||||
* parameters in the OPA_InitStruct.
|
||||
*
|
||||
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
tmp = OPA->CR;
|
||||
tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||
tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||
OPA->CR = tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_StructInit
|
||||
*
|
||||
* @brief Fills each OPA_StructInit member with its reset value.
|
||||
*
|
||||
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
|
||||
{
|
||||
OPA_InitStruct->Mode = OUT_IO_OUT1;
|
||||
OPA_InitStruct->PSEL = CHP0;
|
||||
OPA_InitStruct->NSEL = CHN0;
|
||||
OPA_InitStruct->OPA_NUM = OPA1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified OPA peripheral.
|
||||
*
|
||||
* @param OPA_NUM - Select OPA
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
|
||||
}
|
||||
else
|
||||
{
|
||||
OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
|
||||
}
|
||||
}
|
||||
398
vd960DBN/SRC/Peripheral/src/ch32v20x_pwr.c
Normal file
398
vd960DBN/SRC/Peripheral/src/ch32v20x_pwr.c
Normal file
@@ -0,0 +1,398 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_pwr.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the PWR firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_pwr.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* PWR registers bit mask */
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_DeInit
|
||||
*
|
||||
* @brief Deinitializes the PWR peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_BackupAccessCmd
|
||||
*
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
*
|
||||
* @param NewState - new state of the access to the RTC and backup registers,
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
PWR->CTLR |= (1 << 8);
|
||||
}
|
||||
else
|
||||
{
|
||||
PWR->CTLR &= ~(1 << 8);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_PVDCmd
|
||||
*
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
*
|
||||
* @param NewState - new state of the PVD(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
PWR->CTLR |= (1 << 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
PWR->CTLR &= ~(1 << 4);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_PVDLevelConfig
|
||||
*
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage
|
||||
* Detector(PVD).
|
||||
*
|
||||
* @param PWR_PVDLevel - specifies the PVD detection level
|
||||
* PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
|
||||
* PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
|
||||
* PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
|
||||
* PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
|
||||
* PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
|
||||
* PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
|
||||
* PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
|
||||
* PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= CTLR_PLS_MASK;
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
PWR->CTLR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_WakeUpPinCmd
|
||||
*
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
*
|
||||
* @param NewState - new state of the WakeUp Pin functionality
|
||||
* (ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
PWR->CSR |= (1 << 8);
|
||||
}
|
||||
else
|
||||
{
|
||||
PWR->CSR &= ~(1 << 8);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTOPMode
|
||||
*
|
||||
* @brief Enters STOP mode.
|
||||
*
|
||||
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||
* PWR_Regulator_ON - STOP mode with regulator ON
|
||||
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= CTLR_DS_MASK;
|
||||
tmpreg |= PWR_Regulator;
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
__WFE();
|
||||
}
|
||||
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode
|
||||
*
|
||||
* @brief Enters STANDBY mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
PWR->CTLR |= PWR_CTLR_CWUF;
|
||||
PWR->CTLR |= PWR_CTLR_PDDS;
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
*
|
||||
* @param PWR_FLAG - specifies the flag to check.
|
||||
* PWR_FLAG_WU - Wake Up flag
|
||||
* PWR_FLAG_SB - StandBy flag
|
||||
* PWR_FLAG_PVDO - PVD Output
|
||||
*
|
||||
* @return The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_ClearFlag
|
||||
*
|
||||
* @brief Clears the PWR's pending flags.
|
||||
*
|
||||
* @param PWR_FLAG - specifies the flag to clear.
|
||||
* PWR_FLAG_WU - Wake Up flag
|
||||
* PWR_FLAG_SB - StandBy flag
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
PWR->CTLR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode_RAM
|
||||
*
|
||||
* @brief Enters STANDBY mode with RAM data retention function on.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode_RAM(void)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
|
||||
tmpreg |= PWR_CTLR_CWUF;
|
||||
tmpreg |= PWR_CTLR_PDDS;
|
||||
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
//2K+30K in standby w power.
|
||||
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||
#else
|
||||
//RAM in standby power.
|
||||
tmpreg |= ( ( uint32_t )1 << 16 );
|
||||
|
||||
#endif
|
||||
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode_RAM_LV
|
||||
*
|
||||
* @brief Enters STANDBY mode with RAM data retention function and LV mode on.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode_RAM_LV(void)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
|
||||
tmpreg |= PWR_CTLR_CWUF;
|
||||
tmpreg |= PWR_CTLR_PDDS;
|
||||
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
//2K+30K in standby power.
|
||||
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||
//2K+30K in standby LV .
|
||||
tmpreg |= (0x1 << 20);
|
||||
#else
|
||||
//RAM in standby power.
|
||||
tmpreg |= ( ( uint32_t )1 << 16 );
|
||||
//RAM in standby LV .
|
||||
tmpreg |= ( ( uint32_t )1 << 20 );
|
||||
|
||||
#endif
|
||||
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
|
||||
*
|
||||
* @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
|
||||
tmpreg |= PWR_CTLR_CWUF;
|
||||
tmpreg |= PWR_CTLR_PDDS;
|
||||
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
//2K+30K in standby power (VBAT Enable).
|
||||
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||
#else
|
||||
//RAM in standby w power.
|
||||
tmpreg |= ( ( uint32_t )1 << 18 );
|
||||
|
||||
#endif
|
||||
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
|
||||
*
|
||||
* @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
|
||||
tmpreg |= PWR_CTLR_CWUF;
|
||||
tmpreg |= PWR_CTLR_PDDS;
|
||||
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
//2K+30K in standby power (VBAT Enable).
|
||||
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||
//2K+30K in standby LV .
|
||||
tmpreg |= (0x1 << 20);
|
||||
#else
|
||||
//RAM in standby w power.
|
||||
tmpreg |= ( ( uint32_t )1 << 18 );
|
||||
//RAM in standby LV .
|
||||
tmpreg |= ( ( uint32_t )1 << 20 );
|
||||
|
||||
#endif
|
||||
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTOPMode_RAM_LV
|
||||
*
|
||||
* @brief Enters STOP mode with RAM data retention function and LV mode on.
|
||||
*
|
||||
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||
* PWR_Regulator_ON - STOP mode with regulator ON
|
||||
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= CTLR_DS_MASK;
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
|
||||
|
||||
tmpreg |= (0x1 << 20);
|
||||
#else
|
||||
|
||||
tmpreg |= ( ( uint32_t )1 << 20 );
|
||||
|
||||
#endif
|
||||
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
__WFE();
|
||||
}
|
||||
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
}
|
||||
1061
vd960DBN/SRC/Peripheral/src/ch32v20x_rcc.c
Normal file
1061
vd960DBN/SRC/Peripheral/src/ch32v20x_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
478
vd960DBN/SRC/Peripheral/src/ch32v20x_rtc.c
Normal file
478
vd960DBN/SRC/Peripheral/src/ch32v20x_rtc.c
Normal file
@@ -0,0 +1,478 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_rtc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/06
|
||||
* Description : This file provides all the RTC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_rtc.h"
|
||||
|
||||
/* RTC_Private_Defines */
|
||||
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
|
||||
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified RTC interrupts.
|
||||
*
|
||||
* @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
|
||||
* RTC_IT_OW - Overflow interrupt
|
||||
* RTC_IT_ALR - Alarm interrupt
|
||||
* RTC_IT_SEC - Second interrupt
|
||||
*
|
||||
* @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
|
||||
*/
|
||||
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RTC->CTLRH |= RTC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC->CTLRH &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_EnterConfigMode
|
||||
*
|
||||
* @brief Enters the RTC configuration mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_EnterConfigMode(void)
|
||||
{
|
||||
RTC->CTLRL |= RTC_CTLRL_CNF;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_ExitConfigMode
|
||||
*
|
||||
* @brief Exits from the RTC configuration mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_ExitConfigMode(void)
|
||||
{
|
||||
RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_GetCounter
|
||||
*
|
||||
* @brief Gets the RTC counter value
|
||||
*
|
||||
* @return RTC counter value
|
||||
*/
|
||||
uint32_t RTC_GetCounter(void)
|
||||
{
|
||||
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||
uint16_t low1 = 0, low2 = 0;
|
||||
|
||||
do{
|
||||
high1a = RTC->CNTH;
|
||||
high1b = RTC->CNTH;
|
||||
}while( high1a != high1b );
|
||||
|
||||
do{
|
||||
low1 = RTC->CNTL;
|
||||
low2 = RTC->CNTL;
|
||||
}while( low1 != low2 );
|
||||
|
||||
do{
|
||||
high2a = RTC->CNTH;
|
||||
high2b = RTC->CNTH;
|
||||
}while( high2a != high2b );
|
||||
|
||||
if(high1b != high2b)
|
||||
{
|
||||
do{
|
||||
low1 = RTC->CNTL;
|
||||
low2 = RTC->CNTL;
|
||||
}while( low1 != low2 );
|
||||
}
|
||||
|
||||
return (((uint32_t)high2b << 16) | low2);
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_SetCounter
|
||||
*
|
||||
* @brief Sets the RTC counter value.
|
||||
*
|
||||
* @param CounterValue - RTC counter new value.
|
||||
*
|
||||
* @return RTC counter value
|
||||
*/
|
||||
void RTC_SetCounter(uint32_t CounterValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
RTC->CNTH = CounterValue >> 16;
|
||||
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_SetPrescaler
|
||||
*
|
||||
* @brief Sets the RTC prescaler value
|
||||
*
|
||||
* @param PrescalerValue - RTC prescaler new value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_SetAlarm
|
||||
*
|
||||
* @brief Sets the RTC alarm value
|
||||
*
|
||||
* @param AlarmValue - RTC alarm new value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||
{
|
||||
RTC_EnterConfigMode();
|
||||
RTC->ALRMH = AlarmValue >> 16;
|
||||
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
|
||||
RTC_ExitConfigMode();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_GetDivider
|
||||
*
|
||||
* @brief Gets the RTC divider value
|
||||
*
|
||||
* @return RTC Divider value
|
||||
*/
|
||||
uint32_t RTC_GetDivider(void)
|
||||
{
|
||||
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||
uint16_t low1 = 0, low2 = 0;
|
||||
|
||||
do{
|
||||
high1a = RTC->DIVH;
|
||||
high1b = RTC->DIVH;
|
||||
}while( high1a != high1b );
|
||||
|
||||
do{
|
||||
low1 = RTC->DIVL;
|
||||
low2 = RTC->DIVL;
|
||||
}while( low1 != low2 );
|
||||
|
||||
do{
|
||||
high2a = RTC->DIVH;
|
||||
high2b = RTC->DIVH;
|
||||
}while( high2a != high2b );
|
||||
|
||||
if(high1b != high2b)
|
||||
{
|
||||
do{
|
||||
low1 = RTC->DIVL;
|
||||
low2 = RTC->DIVL;
|
||||
}while( low1 != low2 );
|
||||
}
|
||||
|
||||
return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_WaitForLastTask
|
||||
*
|
||||
* @brief Waits until last write operation on RTC registers has finished
|
||||
* Note-
|
||||
* This function must be called before any write to RTC registers.
|
||||
* @return none
|
||||
*/
|
||||
void RTC_WaitForLastTask(void)
|
||||
{
|
||||
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_WaitForSynchro
|
||||
*
|
||||
* @brief Waits until the RTC registers are synchronized with RTC APB clock
|
||||
* Note-
|
||||
* This function must be called before any read operation after an APB reset
|
||||
* or an APB clock stop.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_WaitForSynchro(void)
|
||||
{
|
||||
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified RTC flag is set or not
|
||||
*
|
||||
* @param RTC_FLAG- specifies the flag to check
|
||||
* RTC_FLAG_RTOFF - RTC Operation OFF flag
|
||||
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||
* RTC_FLAG_OW - Overflow flag
|
||||
* RTC_FLAG_ALR - Alarm flag
|
||||
* RTC_FLAG_SEC - Second flag
|
||||
*
|
||||
* @return The new state of RTC_FLAG (SET or RESET)
|
||||
*/
|
||||
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_ClearFlag
|
||||
*
|
||||
* @brief Clears the RTC's pending flags
|
||||
*
|
||||
* @param RTC_FLAG - specifies the flag to clear
|
||||
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||
* RTC_FLAG_OW - Overflow flag
|
||||
* RTC_FLAG_ALR - Alarm flag
|
||||
* RTC_FLAG_SEC - Second flag
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||
{
|
||||
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified RTC interrupt has occurred or not
|
||||
*
|
||||
* @param RTC_IT - specifies the RTC interrupts sources to check
|
||||
* RTC_FLAG_OW - Overflow interrupt
|
||||
* RTC_FLAG_ALR - Alarm interrupt
|
||||
* RTC_FLAG_SEC - Second interrupt
|
||||
*
|
||||
* @return The new state of the RTC_IT (SET or RESET)
|
||||
*/
|
||||
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
|
||||
if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RTC_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the RTC's interrupt pending bits
|
||||
*
|
||||
* @param RTC_IT - specifies the interrupt pending bit to clear
|
||||
* RTC_FLAG_OW - Overflow interrupt
|
||||
* RTC_FLAG_ALR - Alarm interrupt
|
||||
* RTC_FLAG_SEC - Second interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||
{
|
||||
RTC->CTLRL &= (uint16_t)~RTC_IT;
|
||||
}
|
||||
|
||||
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
|
||||
/*******************************************************************************
|
||||
* @fn Calibration_LSI
|
||||
*
|
||||
* @brief LSI calibration
|
||||
*
|
||||
* @param cali_Lv : calibration level
|
||||
* Level_32 - 1.2ms 1100ppm
|
||||
* Level_64 - 2.2ms 1000ppm
|
||||
* Level_128 - 4.2ms 800ppm
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Calibration_LSI(Cali_LevelTypeDef cali_Lv)
|
||||
{
|
||||
uint32_t i;
|
||||
int32_t cnt_offset;
|
||||
int32_t Freq = 0;
|
||||
uint8_t retry = 0;
|
||||
uint8_t retry_all = 0;
|
||||
uint32_t cnt_32k = 0;
|
||||
Freq = SystemCoreClock;
|
||||
// Coarse tuning
|
||||
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
|
||||
OSC->LSI32K_CAL_CFG |= 0;
|
||||
while(1)
|
||||
{
|
||||
retry_all++;
|
||||
while(1)
|
||||
{
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
cnt_32k = RTC_GetCounter();
|
||||
while(RTC_GetCounter() == cnt_32k);
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 2000 * (Freq / 1000) / CAB_LSIFQ;
|
||||
if(((cnt_offset > -(20 * (Freq / 1000) / 36000)) && (cnt_offset < (20 * (Freq / 1000) / 36000))) || retry > 2)
|
||||
break;
|
||||
retry++;
|
||||
cnt_offset = (cnt_offset > 0) ? (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) + 1) / 2 : (((cnt_offset * 2) / (40 * (Freq / 1000) / 36000)) - 1) / 2;
|
||||
OSC->LSI32K_TUNE += cnt_offset;
|
||||
}
|
||||
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
|
||||
OSC->LSI32K_CAL_CFG |= 2;
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
|
||||
// Fine tuning
|
||||
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
cnt_32k = RTC_GetCounter();
|
||||
while(RTC_GetCounter() == cnt_32k);
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << 2) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
|
||||
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << 2) / 4) * (Freq / 1000) / 36000)) - 1) / 2);
|
||||
if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF))
|
||||
{
|
||||
if(retry_all>2)
|
||||
{
|
||||
OSC->LSI32K_TUNE |= (0xFF<<5);
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset)))
|
||||
{
|
||||
if(retry_all>2)
|
||||
{
|
||||
OSC->LSI32K_TUNE &= 0x1F;
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x7F<<5);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE += (cnt_offset<<5);
|
||||
}
|
||||
OSC->LSI32K_CAL_CFG &= ~RB_OSC_CNT_VLU;
|
||||
OSC->LSI32K_CAL_CFG |= cali_Lv;
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
// Fine tuning
|
||||
// After configuring the fine-tuning parameters, discard the two captured values (software behavior) and judge once, only one time is left here
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_CTRL |= RB_OSC_CAL_EN;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_IF_END;
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
cnt_32k = RTC_GetCounter();
|
||||
while(RTC_GetCounter() == cnt_32k);
|
||||
OSC->LSI32K_CAL_STATR |= RB_OSC_CAL_CNT_OV;
|
||||
while(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END);
|
||||
while(!(OSC->LSI32K_CAL_STATR & RB_OSC_CAL_IF_END));
|
||||
OSC->LSI32K_CAL_CTRL &= ~RB_OSC_CAL_EN;
|
||||
i = OSC->LSI32K_CAL_STATR;
|
||||
cnt_offset = (i & 0x3FFF) + OSC->LSI32K_CAL_OV_CNT * 0x3FFF - 8000 * (1 << cali_Lv) * (Freq / 1000000) / 256 * 1000 / (CAB_LSIFQ / 256);
|
||||
cnt_offset = (cnt_offset > 0) ? ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) + 1) / 2) : ((((cnt_offset * 2 * 100) / (748 * ((1 << cali_Lv) / 4) * (Freq / 1000) / 36000)) - 1) / 2);
|
||||
if((cnt_offset > 0)&&(((OSC->LSI32K_TUNE>>5)+cnt_offset)>0x7FF))
|
||||
{
|
||||
if(retry_all>2)
|
||||
{
|
||||
OSC->LSI32K_TUNE |= (0xFF<<5);
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3FF<<5);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else if((cnt_offset < 0)&&((OSC->LSI32K_TUNE>>5)<(-cnt_offset)))
|
||||
{
|
||||
if(retry_all>2)
|
||||
{
|
||||
OSC->LSI32K_TUNE &= 0x1F;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE = (OSC->LSI32K_TUNE&0x1F)|(0x3F<<5);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
OSC->LSI32K_TUNE += (cnt_offset<<5);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
660
vd960DBN/SRC/Peripheral/src/ch32v20x_spi.c
Normal file
660
vd960DBN/SRC/Peripheral/src/ch32v20x_spi.c
Normal file
@@ -0,0 +1,660 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_spi.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the SPI firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_spi.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CTLR1_SPE_Set ((uint16_t)0x0040)
|
||||
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2S I2SE mask */
|
||||
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
|
||||
|
||||
/* SPI CRCEN mask */
|
||||
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
|
||||
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||
|
||||
/* SPI SSOE mask */
|
||||
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
|
||||
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||
|
||||
/* SPI registers Masks */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||
|
||||
/* SPI or I2S mode selection masks */
|
||||
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||
|
||||
/* I2S clock source selection masks */
|
||||
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_DeInit
|
||||
*
|
||||
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||
{
|
||||
if(SPIx == SPI1)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||
}
|
||||
else if(SPIx == SPI2)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Init
|
||||
*
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the SPI_InitStruct.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
tmpreg = SPIx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||
|
||||
SPIx->CTLR1 = tmpreg;
|
||||
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2S_Init
|
||||
*
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the I2S_InitStruct.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* (configured in I2S mode).
|
||||
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral
|
||||
* configured in I2S mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||
uint32_t tmp = 0;
|
||||
RCC_ClocksTypeDef RCC_Clocks;
|
||||
uint32_t sourceclock = 0;
|
||||
|
||||
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||
SPIx->I2SPR = 0x0002;
|
||||
tmpreg = SPIx->I2SCFGR;
|
||||
|
||||
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||
{
|
||||
i2sodd = (uint16_t)0;
|
||||
i2sdiv = (uint16_t)2;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||
{
|
||||
packetlength = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
packetlength = 2;
|
||||
}
|
||||
|
||||
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||
{
|
||||
tmp = I2S2_CLOCK_SRC;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = I2S3_CLOCK_SRC;
|
||||
}
|
||||
|
||||
RCC_GetClocksFreq(&RCC_Clocks);
|
||||
|
||||
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||
|
||||
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||
{
|
||||
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||
}
|
||||
|
||||
tmp = tmp / 10;
|
||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||
i2sodd = (uint16_t)(i2sodd << 8);
|
||||
}
|
||||
|
||||
if((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||
{
|
||||
i2sdiv = 2;
|
||||
i2sodd = 0;
|
||||
}
|
||||
|
||||
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
|
||||
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
|
||||
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||
SPIx->I2SCFGR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_StructInit
|
||||
*
|
||||
* @brief Fills each SPI_InitStruct member with its default value.
|
||||
*
|
||||
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2S_StructInit
|
||||
*
|
||||
* @brief Fills each I2S_InitStruct member with its default value.
|
||||
*
|
||||
* @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
|
||||
{
|
||||
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified SPI peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_SPE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= CTLR1_SPE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2S_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
|
||||
* enabled or disabled.
|
||||
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
|
||||
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
|
||||
* SPI_I2S_IT_ERR - Error interrupt mask.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||
{
|
||||
uint16_t itpos = 0, itmask = 0;
|
||||
|
||||
itpos = SPI_I2S_IT >> 4;
|
||||
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= (uint16_t)~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
|
||||
* be enabled or disabled.
|
||||
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
|
||||
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= SPI_I2S_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_SendData
|
||||
*
|
||||
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* Data - Data to be transmitted.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
|
||||
{
|
||||
SPIx->DATAR = Data;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* Data - Data to be transmitted.
|
||||
*
|
||||
* @return SPIx->DATAR - The value of the received data.
|
||||
*/
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return SPIx->DATAR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_NSSInternalSoftwareConfig
|
||||
*
|
||||
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* SPI_NSSInternalSoft -
|
||||
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
|
||||
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
|
||||
{
|
||||
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||
{
|
||||
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_SSOutputCmd
|
||||
*
|
||||
* @brief Enables or disables the SS output for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* NewState - new state of the SPIx SS output.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= CTLR2_SSOE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_DataSizeConfig
|
||||
*
|
||||
* @brief Configures the data size for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* SPI_DataSize - specifies the SPI data size.
|
||||
* SPI_DataSize_16b - Set data frame format to 16bit.
|
||||
* SPI_DataSize_8b - Set data frame format to 8bit.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
|
||||
{
|
||||
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||
SPIx->CTLR1 |= SPI_DataSize;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_TransmitCRC
|
||||
*
|
||||
* @brief Transmit the SPIx CRC value.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_CalculateCRC
|
||||
*
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* NewState - new state of the SPIx CRC value calculation.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_GetCRC
|
||||
*
|
||||
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* SPI_CRC - specifies the CRC register to be read.
|
||||
* SPI_CRC_Tx - Selects Tx CRC register.
|
||||
* SPI_CRC_Rx - Selects Rx CRC register.
|
||||
*
|
||||
* @return crcreg: The selected CRC register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
|
||||
{
|
||||
uint16_t crcreg = 0;
|
||||
|
||||
if(SPI_CRC != SPI_CRC_Rx)
|
||||
{
|
||||
crcreg = SPIx->TCRCR;
|
||||
}
|
||||
else
|
||||
{
|
||||
crcreg = SPIx->RCRCR;
|
||||
}
|
||||
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_GetCRCPolynomial
|
||||
*
|
||||
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
*
|
||||
* @return SPIx->CRCR - The CRC Polynomial register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return SPIx->CRCR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_BiDirectionalLineConfig
|
||||
*
|
||||
* @brief Selects the data transfer direction in bi-directional mode
|
||||
* for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* SPI_Direction - specifies the data transfer direction in
|
||||
* bi-directional mode.
|
||||
* SPI_Direction_Tx - Selects Tx transmission direction.
|
||||
* SPI_Direction_Rx - Selects Rx receive direction.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
|
||||
{
|
||||
if(SPI_Direction == SPI_Direction_Tx)
|
||||
{
|
||||
SPIx->CTLR1 |= SPI_Direction_Tx;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= SPI_Direction_Rx;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
|
||||
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
|
||||
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
|
||||
* SPI_I2S_FLAG_BSY - Busy flag.
|
||||
* SPI_I2S_FLAG_OVR - Overrun flag.
|
||||
* SPI_FLAG_MODF - Mode Fault flag.
|
||||
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||
* I2S_FLAG_UDR - Underrun Error flag.
|
||||
* I2S_FLAG_CHSIDE - Channel Side flag.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ClearFlag
|
||||
*
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* SPI_I2S_FLAG - specifies the SPI flag to clear.
|
||||
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||
* Note-
|
||||
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
|
||||
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* - 2 or 3 in I2S mode.
|
||||
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
|
||||
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
|
||||
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
|
||||
* SPI_I2S_IT_OVR - Overrun interrupt.
|
||||
* SPI_IT_MODF - Mode Fault interrupt.
|
||||
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||
* I2S_IT_UDR - Underrun Error interrupt.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
itmask = SPI_I2S_IT >> 4;
|
||||
itmask = 0x01 << itmask;
|
||||
enablestatus = (SPIx->CTLR2 & itmask);
|
||||
|
||||
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1, 2 or 3 in SPI mode.
|
||||
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
|
||||
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||
* Note-
|
||||
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
|
||||
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
|
||||
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
|
||||
* the SPI).
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
uint16_t itpos = 0;
|
||||
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
SPIx->STATR = (uint16_t)~itpos;
|
||||
}
|
||||
2353
vd960DBN/SRC/Peripheral/src/ch32v20x_tim.c
Normal file
2353
vd960DBN/SRC/Peripheral/src/ch32v20x_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
740
vd960DBN/SRC/Peripheral/src/ch32v20x_usart.c
Normal file
740
vd960DBN/SRC/Peripheral/src/ch32v20x_usart.c
Normal file
@@ -0,0 +1,740 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_usart.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/06
|
||||
* Description : This file provides all the USART firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_usart.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* USART_Private_Defines */
|
||||
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
|
||||
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
|
||||
|
||||
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
|
||||
|
||||
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */
|
||||
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
|
||||
|
||||
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
|
||||
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
|
||||
|
||||
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
|
||||
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */
|
||||
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */
|
||||
|
||||
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
|
||||
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
|
||||
|
||||
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
|
||||
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
|
||||
|
||||
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
|
||||
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
|
||||
|
||||
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
|
||||
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */
|
||||
|
||||
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
|
||||
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
|
||||
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
|
||||
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
|
||||
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DeInit
|
||||
*
|
||||
* @brief Deinitializes the USARTx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DeInit(USART_TypeDef *USARTx)
|
||||
{
|
||||
if(USARTx == USART1)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART2)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART3)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
|
||||
}
|
||||
else if(USARTx == UART4)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Init
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral according to the specified
|
||||
* parameters in the USART_InitStruct.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
|
||||
* USART_InitStruct - pointer to a USART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00, apbclock = 0x00;
|
||||
uint32_t integerdivider = 0x00;
|
||||
uint32_t fractionaldivider = 0x00;
|
||||
uint32_t usartxbase = 0;
|
||||
RCC_ClocksTypeDef RCC_ClocksStatus;
|
||||
|
||||
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
|
||||
{
|
||||
}
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_STOP_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
|
||||
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
tmpreg = USARTx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
|
||||
USART_InitStruct->USART_Mode;
|
||||
USARTx->CTLR1 = (uint16_t)tmpreg;
|
||||
|
||||
tmpreg = USARTx->CTLR3;
|
||||
tmpreg &= CTLR3_CLEAR_Mask;
|
||||
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
|
||||
USARTx->CTLR3 = (uint16_t)tmpreg;
|
||||
|
||||
RCC_GetClocksFreq(&RCC_ClocksStatus);
|
||||
|
||||
if(usartxbase == USART1_BASE)
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
|
||||
}
|
||||
else
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
|
||||
}
|
||||
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
|
||||
tmpreg = (integerdivider / 100) << 4;
|
||||
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
|
||||
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
|
||||
USARTx->BRR = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_StructInit
|
||||
*
|
||||
* @brief Fills each USART_InitStruct member with its default value.
|
||||
*
|
||||
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
USART_InitStruct->USART_BaudRate = 9600;
|
||||
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStruct->USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStruct->USART_Parity = USART_Parity_No;
|
||||
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockInit
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral Clock according to the
|
||||
* specified parameters in the USART_ClockInitStruct .
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||
* structure that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
|
||||
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockStructInit
|
||||
*
|
||||
* @brief Fills each USART_ClockStructInit member with its default value.
|
||||
*
|
||||
* @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||
* structure which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
|
||||
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
|
||||
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
|
||||
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified USART peripheral.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_UE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_UE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified USART interrupts.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Transmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
* USART_IT_ERR - Error interrupt.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
|
||||
{
|
||||
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
|
||||
uint32_t usartxbase = 0x00;
|
||||
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itpos = USART_IT & IT_Mask;
|
||||
itmask = (((uint32_t)0x01) << itpos);
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
usartxbase += 0x0C;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
usartxbase += 0x10;
|
||||
}
|
||||
else
|
||||
{
|
||||
usartxbase += 0x14;
|
||||
}
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase &= ~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the USART DMA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_DMAReq - specifies the DMA request.
|
||||
* USART_DMAReq_Tx - USART DMA transmit request.
|
||||
* USART_DMAReq_Rx - USART DMA receive request.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= USART_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetAddress
|
||||
*
|
||||
* @brief Sets the address of the USART node.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_Address - Indicates the address of the USART node.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_Address_Mask;
|
||||
USARTx->CTLR2 |= USART_Address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_WakeUpConfig
|
||||
*
|
||||
* @brief Selects the USART WakeUp method.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_WakeUp - specifies the USART wakeup method.
|
||||
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
|
||||
* USART_WakeUp_AddressMark - WakeUp by an address mark.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
|
||||
USARTx->CTLR1 |= USART_WakeUp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiverWakeUpCmd
|
||||
*
|
||||
* @brief Determines if the USART is in mute mode or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_RWU_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_RWU_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINBreakDetectLengthConfig
|
||||
*
|
||||
* @brief Sets the USART LIN Break detection length.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_LINBreakDetectLength - specifies the LIN break detection length.
|
||||
* USART_LINBreakDetectLength_10b - 10-bit break detection.
|
||||
* USART_LINBreakDetectLength_11b - 11-bit break detection.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
|
||||
USARTx->CTLR2 |= USART_LINBreakDetectLength;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINCmd
|
||||
*
|
||||
* @brief Enables or disables the USART LIN mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR2 |= CTLR2_LINEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendData
|
||||
*
|
||||
* @brief Transmits single data through the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* Data - the data to transmit.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
|
||||
{
|
||||
USARTx->DATAR = (Data & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
*
|
||||
* @return The received data.
|
||||
*/
|
||||
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
|
||||
{
|
||||
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendBreak
|
||||
*
|
||||
* @brief Transmits break characters.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendBreak(USART_TypeDef *USARTx)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_SBK_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetGuardTime
|
||||
*
|
||||
* @brief Sets the specified USART guard time.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_GuardTime - specifies the guard time.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
|
||||
{
|
||||
USARTx->GPR &= GPR_LSB_Mask;
|
||||
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetPrescaler
|
||||
*
|
||||
* @brief Sets the system clock prescaler.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_Prescaler - specifies the prescaler clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
|
||||
{
|
||||
USARTx->GPR &= GPR_MSB_Mask;
|
||||
USARTx->GPR |= USART_Prescaler;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Smart Card mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_SCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardNACKCmd
|
||||
*
|
||||
* @brief Enables or disables NACK transmission.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_NACK_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_NACK_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_HalfDuplexCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Half Duplex communication.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDAConfig
|
||||
*
|
||||
* @brief Configures the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IrDAMode - specifies the IrDA mode.
|
||||
* USART_IrDAMode_LowPower.
|
||||
* USART_IrDAMode_Normal.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
|
||||
USARTx->CTLR3 |= USART_IrDAMode;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDACmd
|
||||
*
|
||||
* @brief Enables or disables the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_IREN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IREN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART flag is set or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to check.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TXE - Transmit data register empty flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* USART_FLAG_IDLE - Idle Line detection flag.
|
||||
* USART_FLAG_ORE - OverRun Error flag.
|
||||
* USART_FLAG_NE - Noise Error flag.
|
||||
* USART_FLAG_FE - Framing Error flag.
|
||||
* USART_FLAG_PE - Parity Error flag.
|
||||
*
|
||||
* @return bitstatus: SET or RESET
|
||||
*/
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
|
||||
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearFlag
|
||||
*
|
||||
* @brief Clears the USARTx's pending flags.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to clear.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
|
||||
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
|
||||
* - RXNE flag can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
|
||||
* to USART_DATAR register (USART_SendData()).
|
||||
* - TXE flag is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
|
||||
USARTx->STATR = (uint16_t)~USART_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART interrupt has occurred or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt source to check.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Tansmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
|
||||
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
|
||||
* USART_IT_NE - Noise Error interrupt.
|
||||
* USART_IT_FE - Framing Error interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
*
|
||||
* @return bitstatus: SET or RESET.
|
||||
*/
|
||||
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itmask = USART_IT & IT_Mask;
|
||||
itmask = (uint32_t)0x01 << itmask;
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
itmask &= USARTx->CTLR1;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
itmask &= USARTx->CTLR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
itmask &= USARTx->CTLR3;
|
||||
}
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
bitpos = (uint32_t)0x01 << bitpos;
|
||||
bitpos &= USARTx->STATR;
|
||||
|
||||
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the USARTx's interrupt pending bits.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the interrupt pending bit to clear.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) pending bits are cleared by
|
||||
* software sequence: a read operation to USART_STATR register
|
||||
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC pending bit can be also cleared by software sequence: a read
|
||||
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
|
||||
* operation to USART_DATAR register (USART_SendData()).
|
||||
* - TXE pending bit is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint16_t bitpos = 0x00, itmask = 0x00;
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
|
||||
USARTx->STATR = (uint16_t)~itmask;
|
||||
}
|
||||
141
vd960DBN/SRC/Peripheral/src/ch32v20x_wwdg.c
Normal file
141
vd960DBN/SRC/Peripheral/src/ch32v20x_wwdg.c
Normal file
@@ -0,0 +1,141 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v20x_wwdg.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : This file provides all the WWDG firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v20x_wwdg.h"
|
||||
#include "ch32v20x_rcc.h"
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
|
||||
|
||||
/* CFGR register bit mask */
|
||||
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_Mask ((uint8_t)0x7F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_DeInit
|
||||
*
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetPrescaler
|
||||
*
|
||||
* @brief Sets the WWDG Prescaler
|
||||
*
|
||||
* @param WWDG_Prescaler - specifies the WWDG Prescaler
|
||||
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
|
||||
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
|
||||
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
|
||||
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
WWDG->CFGR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetWindowValue
|
||||
*
|
||||
* @brief Sets the WWDG window value
|
||||
*
|
||||
* @param WindowValue - specifies the window value to be compared to the
|
||||
* downcounter,which must be lower than 0x80
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = WWDG->CFGR & CFGR_W_Mask;
|
||||
|
||||
tmpreg |= WindowValue & (uint32_t)BIT_Mask;
|
||||
|
||||
WWDG->CFGR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_EnableIT
|
||||
*
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI)
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
WWDG->CFGR |= (1 << 9);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetCounter
|
||||
*
|
||||
* @brief Sets the WWDG counter value
|
||||
*
|
||||
* @param Counter - specifies the watchdog counter value,which must be a
|
||||
* number between 0x40 and 0x7F
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
WWDG->CTLR = Counter & BIT_Mask;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_Enable
|
||||
*
|
||||
* @brief Enables WWDG and load the counter value
|
||||
*
|
||||
* @param Counter - specifies the watchdog counter value,which must be a
|
||||
* number between 0x40 and 0x7F
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
WWDG->CTLR = CTLR_WDGA_Set | Counter;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not
|
||||
*
|
||||
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(WWDG->STATR);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_ClearFlag
|
||||
*
|
||||
* @brief Clears Early Wakeup interrupt flag
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->STATR = (uint32_t)RESET;
|
||||
}
|
||||
Reference in New Issue
Block a user