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refactor(vd960Loop): 算法回退到 DLD154V4B，四通道适配

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- 用 DLD154V4B vd1_task/per_channel 替换 vds_task 复杂算法
- 移除 FUNCTION_B/二次判断/快速变化/多重确认等增强特性
- 保留平坦性离开算法 (CN200910309382)，每通道独立状态
- 灵敏度表改为 DLD154V4B 4级: {216,108,36,10} / {108,72,18,9}
- 清理废弃类型: FltHistoryManager, Loop_ACS_Info, StageRangeConfig 等
- 首次添加 vd960DBN 完整源码
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wangfq
2026-06-25 16:21:57 +08:00
parent 6fd4e564e3
commit 95808f9f25
966 changed files with 406958 additions and 84 deletions
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815
vd960Loop/libraries/drivers/src/at32f421_adc.c Normal file
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/**
**************************************************************************
* @file at32f421_adc.c
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
#ifdef ADC_MODULE_ENABLED
/** @defgroup ADC_private_functions
* @{
*/
/**
* @brief deinitialize the adc peripheral registers to their default reset values.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_reset(adc_type *adc_x)
{
if(adc_x == ADC1)
{
crm_periph_reset(CRM_ADC1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_ADC1_PERIPH_RESET, FALSE);
}
}
/**
* @brief enable or disable the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of a/d converter.
* this parameter can be: TRUE or FALSE.
* note:after adc ready,user set adcen bit will cause ordinary conversion
* @retval none
*/
void adc_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.adcen = new_state;
}
/**
* @brief adc base default para init.
* @param sequence_mode: set the state of adc sequence mode.
* this parameter can be:TRUE or FALSE
* @param repeat_mode: set the state of adc repeat conversion mode.
* this parameter can be:TRUE or FALSE
* @param data_align: set the state of adc data alignment.
* this parameter can be one of the following values:
* - ADC_RIGHT_ALIGNMENT
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0x10)
* @retval none
*/
void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
{
adc_base_struct->sequence_mode = FALSE;
adc_base_struct->repeat_mode = FALSE;
adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
adc_base_struct->ordinary_channel_length = 1;
}
/**
* @brief initialize the adc peripheral according to the specified parameters.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param sequence_mode: set the state of adc sequence mode.
* this parameter can be:TRUE or FALSE
* @param repeat_mode: set the state of adc repeat conversion mode.
* this parameter can be:TRUE or FALSE
* @param data_align: set the state of adc data alignment.
* this parameter can be one of the following values:
* - ADC_RIGHT_ALIGNMENT
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0x10)
* @retval none
*/
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
{
adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
}
/**
* @brief enable or disable the adc dma transfer.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of the adc dma transfer.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.ocdmaen = new_state;
}
/**
* @brief enable or disable the specified adc interrupts.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_int: specifies the adc interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - ADC_VMOR_INT
* - ADC_CCE_INT
* - ADC_PCCE_INT
* @param new_state: new state of the specified adc interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
{
if(new_state == TRUE)
{
adc_x->ctrl1 |= adc_int;
}
else if(new_state == FALSE)
{
adc_x->ctrl1 &= ~adc_int;
}
}
/**
* @brief initialize calibration register of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_calibration_init(adc_type *adc_x)
{
adc_x->ctrl2_bit.adcalinit = TRUE;
}
/**
* @brief get calibration register's initialize status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of reset calibration register status(SET or RESET).
*/
flag_status adc_calibration_init_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.adcalinit)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief start calibration process of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_calibration_start(adc_type *adc_x)
{
adc_x->ctrl2_bit.adcal = TRUE;
}
/**
* @brief get calibration status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of calibration status(SET or RESET).
*/
flag_status adc_calibration_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.adcal)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_voltage_monitoring: choose the adc_voltage_monitoring config.
* this parameter can be one of the following values:
* - ADC_VMONITOR_SINGLE_ORDINARY
* - ADC_VMONITOR_SINGLE_PREEMPT
* - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
* - ADC_VMONITOR_ALL_ORDINARY
* - ADC_VMONITOR_ALL_PREEMPT
* - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
* - ADC_VMONITOR_NONE
* @retval none
*/
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
{
adc_x->ctrl1_bit.ocvmen = FALSE;
adc_x->ctrl1_bit.pcvmen = FALSE;
adc_x->ctrl1_bit.vmsgen = FALSE;
adc_x->ctrl1 |= adc_voltage_monitoring;
}
/**
* @brief set voltage monitoring's high and low thresholds value of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_high_threshold: voltage monitoring's high thresholds value.
* this parameter can be:
* - (0x000~0xFFF)
* @param adc_low_threshold: voltage monitoring's low thresholds value.
* this parameter can be:
* - (0x000~0xFFF)
* @retval none
*/
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
{
adc_x->vmhb_bit.vmhb = adc_high_threshold;
adc_x->vmlb_bit.vmlb = adc_low_threshold;
}
/**
* @brief select the voltage monitoring's channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @retval none
*/
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
{
adc_x->ctrl1_bit.vmcsel = adc_channel;
}
/**
* @brief set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @param adc_sequence: set rank in the ordinary group sequencer.
* this parameter must be:
* - between 1 to 16
* @param adc_sampletime: set the sampletime of adc channel.
* this parameter can be one of the following values:
* - ADC_SAMPLETIME_1_5
* - ADC_SAMPLETIME_7_5
* - ADC_SAMPLETIME_13_5
* - ADC_SAMPLETIME_28_5
* - ADC_SAMPLETIME_41_5
* - ADC_SAMPLETIME_55_5
* - ADC_SAMPLETIME_71_5
* - ADC_SAMPLETIME_239_5
* @retval none
*/
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint32_t tmp_reg;
if(adc_channel < ADC_CHANNEL_10)
{
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
if(adc_sequence >= 13)
{
tmp_reg = adc_x->osq1;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
adc_x->osq1 = tmp_reg;
}
else if(adc_sequence >= 7)
{
tmp_reg = adc_x->osq2;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
adc_x->osq2 = tmp_reg;
}
else
{
tmp_reg = adc_x->osq3;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
adc_x->osq3 = tmp_reg;
}
}
/**
* @brief set preempt channel lenghth of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel_lenght: set the adc preempt channel lenghth.
* this parameter can be:
* - (0x1~0x4)
* @retval none
*/
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
{
adc_x->psq_bit.pclen = adc_channel_lenght - 1;
}
/**
* @brief configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @param adc_sequence: set rank in the preempt group sequencer.
* this parameter must be:
* - between 1 to 4
* @param adc_sampletime: config the sampletime of adc channel.
* this parameter can be one of the following values:
* - ADC_SAMPLETIME_1_5
* - ADC_SAMPLETIME_7_5
* - ADC_SAMPLETIME_13_5
* - ADC_SAMPLETIME_28_5
* - ADC_SAMPLETIME_41_5
* - ADC_SAMPLETIME_55_5
* - ADC_SAMPLETIME_71_5
* - ADC_SAMPLETIME_239_5
* @retval none
*/
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint32_t tmp_reg;
uint8_t sequence_index;
if(adc_channel < ADC_CHANNEL_10)
{
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
switch(sequence_index)
{
case 1:
adc_x->psq_bit.psn1 = adc_channel;
break;
case 2:
adc_x->psq_bit.psn2 = adc_channel;
break;
case 3:
adc_x->psq_bit.psn3 = adc_channel;
break;
case 4:
adc_x->psq_bit.psn4 = adc_channel;
break;
default:
break;
}
}
/**
* @brief enable or disable the ordinary channel's external trigger and
* set external trigger event of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_ordinary_trig: select the external trigger event.
* this parameter can be one of the following values:
* adc1
* - ADC12_ORDINARY_TRIG_TMR1CH1 - ADC12_ORDINARY_TRIG_TMR1CH2 - ADC12_ORDINARY_TRIG_TMR1CH3
* - ADC12_ORDINARY_TRIG_TMR3TRGOUT - ADC12_ORDINARY_TRIG_TMR15CH1 - ADC12_ORDINARY_TRIG_EXINT11 - ADC12_ORDINARY_TRIG_SOFTWARE
* @param new_state: new state of ordinary channel's external trigger.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state)
{
if(adc_ordinary_trig > 7)
{
adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7;
}
else
{
adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7;
}
adc_x->ctrl2_bit.octen = new_state;
}
/**
* @brief enable or disable the preempt channel's external trigger and
* set external trigger event of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_trig: select the external trigger event.
* this parameter can be one of the following values:
* adc1
* - ADC12_PREEMPT_TRIG_TMR1TRGOUT - ADC12_PREEMPT_TRIG_TMR1CH4
* - ADC12_PREEMPT_TRIG_TMR3CH4 - ADC12_PREEMPT_TRIG_TMR15TRGOUT - ADC12_PREEMPT_TRIG_EXINT15 - ADC12_PREEMPT_TRIG_SOFTWARE
* @param new_state: new state of preempt channel's external trigger.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state)
{
if(adc_preempt_trig > 7)
{
adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7;
}
else
{
adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7;
}
adc_x->ctrl2_bit.pcten = new_state;
}
/**
* @brief set preempt channel's conversion value offset of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_channel: select the preempt channel.
* this parameter can be one of the following values:
* - ADC_PREEMPT_CHANNEL_1
* - ADC_PREEMPT_CHANNEL_2
* - ADC_PREEMPT_CHANNEL_3
* - ADC_PREEMPT_CHANNEL_4
* @param adc_offset_value: set the adc preempt channel's conversion value offset.
* this parameter can be:
* - (0x000~0xFFF)
* @retval none
*/
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
{
switch(adc_preempt_channel)
{
case ADC_PREEMPT_CHANNEL_1:
adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_2:
adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_3:
adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_4:
adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
break;
default:
break;
}
}
/**
* @brief set partitioned mode channel count of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel_count: configure the adc partitioned mode channel count.
* this parameter can be:
* - (0x1~0x8)
* @retval none
*/
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
{
adc_x->ctrl1_bit.ocpcnt = adc_channel_count - 1;
}
/**
* @brief enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of ordinary channel's partitioned mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.ocpen = new_state;
}
/**
* @brief enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of preempt channel's partitioned mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.pcpen = new_state;
}
/**
* @brief enable or disable automatic preempt group conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of automatic preempt group conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.pcautoen = new_state;
}
/**
* @brief enable or disable the temperature sensor and vintrv channel.
* @param new_state: new state of Internal temperature sensor and vintrv.
* this parameter can be: TRUE or FALSE.
* note:this bit is present only in adc1
* @retval none
*/
void adc_tempersensor_vintrv_enable(confirm_state new_state)
{
ADC1->ctrl2_bit.itsrven = new_state;
}
/**
* @brief enable or disable ordinary software start conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of ordinary software start conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.ocswtrg = new_state;
}
/**
* @brief get ordinary software start conversion status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of ordinary software start conversion status(SET or RESET).
*/
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.ocswtrg)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief enable or disable preempt software start conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of preempt software start conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.pcswtrg = new_state;
}
/**
* @brief get preempt software start conversion status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of preempt software start conversion status(SET or RESET).
*/
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.pcswtrg)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief return the last conversion data for ordinary channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the last conversion data for ordinary channel.
*/
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
{
return (uint16_t)(adc_x->odt_bit.odt);
}
/**
* @brief return the conversion data for selection preempt channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_channel: select the preempt channel.
* this parameter can be one of the following values:
* - ADC_PREEMPT_CHANNEL_1
* - ADC_PREEMPT_CHANNEL_2
* - ADC_PREEMPT_CHANNEL_3
* - ADC_PREEMPT_CHANNEL_4
* @retval the conversion data for selection preempt channel.
*/
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
{
uint16_t preempt_conv_data_index = 0;
switch(adc_preempt_channel)
{
case ADC_PREEMPT_CHANNEL_1:
preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
break;
case ADC_PREEMPT_CHANNEL_2:
preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
break;
case ADC_PREEMPT_CHANNEL_3:
preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
break;
case ADC_PREEMPT_CHANNEL_4:
preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
break;
default:
break;
}
return preempt_conv_data_index;
}
/**
* @brief get flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be one of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG
* - ADC_PCCE_FLAG
* - ADC_PCCS_FLAG(no interrupt associated)
* - ADC_OCCS_FLAG(no interrupt associated)
* @retval the new state of adc flag status(SET or RESET).
*/
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
{
flag_status status = RESET;
if((adc_x->sts & adc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be one of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG
* - ADC_PCCE_FLAG
* @retval the new state of adc flag status(SET or RESET).
*/
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
{
flag_status status = RESET;
switch(adc_flag)
{
case ADC_VMOR_FLAG:
if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
{
status = SET;
}
break;
case ADC_CCE_FLAG:
if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien)
{
status = SET;
}
break;
case ADC_PCCE_FLAG:
if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
{
status = SET;
}
break;
default:
break;
}
return status;
}
/**
* @brief clear flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be any combination of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG(also can clear by reading the adc_x->odt)
* - ADC_PCCE_FLAG
* - ADC_PCCS_FLAG
* - ADC_OCCS_FLAG
* @retval none
*/
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
{
adc_x->sts = ~adc_flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_cmp.c
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CMP
* @brief CMP driver modules
* @{
*/
#ifdef CMP_MODULE_ENABLED
/** @defgroup CMP_private_functions
* @{
*/
#define CMP_CTRLSTS1_CLEAR_MASK ((uint32_t)0x00039C7C)
#define CMP_INPINPUT_CLEAR_MASK ((uint32_t)0x00000180)
#define CMP_HIGH_PULSE_CLEAR_MASK ((uint16_t)0x003F)
#define CMP_LOW_PULSE_CLEAR_MASK ((uint16_t)0x003F)
/**
* @brief reset the cmp register
* @param none
* @retval none
*/
void cmp_reset(void)
{
crm_periph_reset(CRM_CMP_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_CMP_PERIPH_RESET, FALSE);
}
/**
* @brief initialize the cmp peripheral
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION
* @param cmp_init_struct: pointer to cmp init structure
* @retval none
*/
void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct)
{
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpninvsel = cmp_init_struct->cmp_non_inverting;
CMP->ctrlsts_bit.cmpinvsel = cmp_init_struct->cmp_inverting;
CMP->ctrlsts_bit.cmpssel = cmp_init_struct->cmp_speed;
CMP->ctrlsts_bit.cmptag = cmp_init_struct->cmp_output;
CMP->ctrlsts_bit.cmpp = cmp_init_struct->cmp_polarity;
CMP->ctrlsts_bit.cmphyst = cmp_init_struct->cmp_hysteresis;
}
}
/**
* @brief fill each cmp_init_type member with its default value.
* @param cmp_init_type : pointer to a cmp_init_type structure
* which will be initialized.
* @retval none
*/
void cmp_default_para_init(cmp_init_type *cmp_init_struct)
{
/* reset cmp init structure parameters values */
cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1;
cmp_init_struct->cmp_inverting = CMP_INVERTING_1_4VREFINT;
cmp_init_struct->cmp_speed = CMP_SPEED_FAST;
cmp_init_struct->cmp_output = CMP_OUTPUT_NONE;
cmp_init_struct->cmp_polarity = CMP_POL_NON_INVERTING;
cmp_init_struct->cmp_hysteresis = CMP_HYSTERESIS_NONE;
}
/**
* @brief enable or disable cmp
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state)
{
/* cmp enable */
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpen = new_state;
}
}
/**
* @brief enable or disable cmp input shift
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_input_shift_enable(confirm_state new_state)
{
CMP->ctrlsts_bit.cmpis = new_state;
}
/**
* @brief get cmp output value
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @retval cmp output value
*/
uint32_t cmp_output_value_get(cmp_sel_type cmp_sel)
{
uint32_t cmpout = 0x0;
if(cmp_sel == CMP1_SELECTION)
{
cmpout = CMP->ctrlsts_bit.cmpvalue;
}
/* return the comparator output level */
return (uint32_t)(cmpout);
}
/**
* @brief enable cmp write protect
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @retval none
*/
void cmp_write_protect_enable(cmp_sel_type cmp_sel)
{
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpwp = TRUE;
}
}
/**
* @brief configure cmp glitch filter
* @param high_pulse_cnt: cmp high pulse count.
* this parameter must be a value between 0x00 and 0x3f
* @param low_pulse_cnt: cmp low pulse count.
* this parameter must be a value between 0x00 and 0x3f
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_filter_config(uint16_t high_pulse_cnt, uint16_t low_pulse_cnt, confirm_state new_state)
{
if (new_state != FALSE)
{
/* enable the glitch filter */
CMP->g_filter_en_bit.gfe = TRUE;
/* write to cmp high_pulse and low_pulse */
CMP->low_pulse_bit.l_pulse_cnt = low_pulse_cnt;
CMP->high_pulse_bit.h_pulse_cnt = high_pulse_cnt;
}
else
{
/* disable the glitch filter */
CMP->g_filter_en_bit.gfe = FALSE;
/* reset the h_pulse_cnt and l_pulse_cnt bits */
CMP->low_pulse_bit.l_pulse_cnt = low_pulse_cnt;
CMP->high_pulse_bit.h_pulse_cnt = high_pulse_cnt;
}
}
/**
* @brief configure cmp blanking source.
* @param blank_sel: cmp blanking source
* this parameter can be one of the following values:
* - CMP_BLANKING_NONE
* - CMP_BLANKING_TMR1_CH4
* - CMP_BLANKING_TMR3_CH3
* - CMP_BLANKING_TMR15_CH2
* - CMP_BLANKING_TMR15_CH1
* @retval none
*/
void cmp_blanking_config(cmp_blanking_type blank_sel)
{
CMP->ctrlsts_bit.cmpblanking = blank_sel;
}
/**
* @brief configure cmp scale voltage and voltage bridge
* @param scal_brg: cmp scal&brg configure
* this parameter can be one of the following values:
* - CMP_SCAL_BRG_00: vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 0v
* - CMP_SCAL_BRG_10: vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 1.2v
* - CMP_SCAL_BRG_11: vrefint = 1.2v, 3/4 vrefint = 0.9v, 1/2 vrefint = 0.6v, 1/4 vrefint = 0.3v
* @retval none
*/
void cmp_scal_brg_config(cmp_scal_brg_type scal_brg)
{
uint32_t tmp_scal = 0, tmp_brg = 0;
tmp_scal = scal_brg >> 1;
tmp_brg = scal_brg & 0x01;
CMP->ctrlsts_bit.scalen = tmp_scal;
CMP->ctrlsts_bit.brgen = tmp_brg;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_crc.c
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
#ifdef CRC_MODULE_ENABLED
/** @defgroup CRC_private_functions
* @{
*/
/**
* @brief reset the crc data register.
* @param none
* @retval none
*/
void crc_data_reset(void)
{
/* reset crc generator */
CRC->ctrl_bit.rst = 0x1;
}
/**
* @brief compute the 32-bit crc of a given data word(32-bit).
* @param data: data word(32-bit) to compute its crc
* @retval 32-bit crc
*/
uint32_t crc_one_word_calculate(uint32_t data)
{
CRC->dt = data;
return (CRC->dt);
}
/**
* @brief compute the 32-bit crc of a given buffer of data word(32-bit).
* @param pbuffer: pointer to the buffer containing the data to be computed
* @param length: length of the buffer to be computed
* @retval 32-bit crc
*/
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
{
uint32_t index = 0;
for(index = 0; index < length; index++)
{
CRC->dt = pbuffer[index];
}
return (CRC->dt);
}
/**
* @brief return the current crc value.
* @param none
* @retval 32-bit crc
*/
uint32_t crc_data_get(void)
{
return (CRC->dt);
}
/**
* @brief store a 8-bit data in the common data register.
* @param cdt_value: 8-bit value to be stored in the common data register
* @retval none
*/
void crc_common_data_set(uint8_t cdt_value)
{
CRC->cdt_bit.cdt = cdt_value;
}
/**
* @brief return the 8-bit data stored in the common data register
* @param none
* @retval 8-bit value of the common data register
*/
uint8_t crc_common_data_get(void)
{
return (CRC->cdt_bit.cdt);
}
/**
* @brief set the 32-bit initial data of crc
* @param value: initial data
* @retval none
*/
void crc_init_data_set(uint32_t value)
{
CRC->idt = value;
}
/**
* @brief control the reversal of the bit order in the input data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_INPUT_NO_AFFECTE
* - CRC_REVERSE_INPUT_BY_BYTE
* - CRC_REVERSE_INPUT_BY_HALFWORD
* - CRC_REVERSE_INPUT_BY_WORD
* @retval none.
*/
void crc_reverse_input_data_set(crc_reverse_input_type value)
{
CRC->ctrl_bit.revid = value;
}
/**
* @brief control the reversal of the bit order in the output data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_OUTPUT_NO_AFFECTE
* - CRC_REVERSE_OUTPUT_DATA
* @retval none.
*/
void crc_reverse_output_data_set(crc_reverse_output_type value)
{
CRC->ctrl_bit.revod = value;
}
/**
* @brief config crc polynomial value
* @param value
* 32-bit new data of crc poly value
* @retval none.
*/
void crc_poly_value_set(uint32_t value)
{
CRC->poly = value;
}
/**
* @brief return crc polynomial value
* @param none
* @retval 32-bit value of the polynomial value.
*/
uint32_t crc_poly_value_get(void)
{
return (CRC->poly);
}
/**
* @brief config crc polynomial data size
* @param size
* this parameter can be one of the following values:
* - CRC_POLY_SIZE_32B
* - CRC_POLY_SIZE_16B
* - CRC_POLY_SIZE_8B
* - CRC_POLY_SIZE_7B
* @retval none.
*/
void crc_poly_size_set(crc_poly_size_type size)
{
CRC->ctrl_bit.poly_size = size;
}
/**
* @brief return crc polynomial data size
* @param none
* @retval polynomial data size.
*/
crc_poly_size_type crc_poly_size_get(void)
{
return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_crm.c
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CRM
* @brief CRM driver modules
* @{
*/
#ifdef CRM_MODULE_ENABLED
/** @defgroup CRM_private_functions
* @{
*/
/**
* @brief reset the crm register
* @param none
* @retval none
*/
void crm_reset(void)
{
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = TRUE;
/* wait hick stable */
while(CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
/* reset pllfr, pllms, pllns and pllfref bits */
CRM->pll = (0x00001F10U);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0x00100000;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000;
}
/**
* @brief enable or disable crm low speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_lext_bypass(confirm_state new_state)
{
CRM->bpdc_bit.lextbyps = new_state;
}
/**
* @brief enable or disable crm high speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_hext_bypass(confirm_state new_state)
{
CRM->ctrl_bit.hextbyps = new_state;
}
/**
* @brief get crm flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_HICK_STABLE_FLAG
* - CRM_HEXT_STABLE_FLAG
* - CRM_PLL_STABLE_FLAG
* - CRM_LEXT_STABLE_FLAG
* - CRM_LICK_STABLE_FLAG
* - CRM_NRST_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_flag_get(uint32_t flag)
{
flag_status status = RESET;
if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get crm interrupt flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_interrupt_flag_get(uint32_t flag)
{
flag_status status = RESET;
switch(flag)
{
case CRM_LICK_READY_INT_FLAG:
if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien)
{
status = SET;
}
break;
case CRM_LEXT_READY_INT_FLAG:
if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien)
{
status = SET;
}
break;
case CRM_HICK_READY_INT_FLAG:
if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien)
{
status = SET;
}
break;
case CRM_HEXT_READY_INT_FLAG:
if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien)
{
status = SET;
}
break;
case CRM_PLL_READY_INT_FLAG:
if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien)
{
status = SET;
}
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden)
{
status = SET;
}
break;
}
return status;
}
/**
* @brief wait for hext stable
* @param none
* @retval error_status (ERROR or SUCCESS)
*/
error_status crm_hext_stable_wait(void)
{
uint32_t stable_cnt = 0;
error_status status = ERROR;
while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
{
stable_cnt ++;
}
if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
return status;
}
/**
* @brief set the hick trimming value
* @param trim_value (0x00~0x3F)
* @retval none
*/
void crm_hick_clock_trimming_set(uint8_t trim_value)
{
CRM->ctrl_bit.hicktrim = trim_value;
}
/**
* @brief set the crm calibration value
* @param cali_value (0x00~0xFF)
* @retval none
*/
void crm_hick_clock_calibration_set(uint8_t cali_value)
{
/* enable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x5A;
/* write hick calibration value */
CRM->ctrl_bit.hickcal = cali_value;
/* disable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x0;
}
/**
* @brief enable or disable the peripheral clock
* @param value
* this parameter can be one of the following values:
* - CRM_DMA1_PERIPH_CLOCK - CRM_CRC_PERIPH_CLOCK - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK
* - CRM_GPIOC_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_SCFG_PERIPH_CLOCK - CRM_CMP_PERIPH_CLOCK
* - CRM_ADC1_PERIPH_CLOCK - CRM_TMR1_PERIPH_CLOCK - CRM_SPI1_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK
* - CRM_TMR15_PERIPH_CLOCK - CRM_TMR16_PERIPH_CLOCK - CRM_TMR17_PERIPH_CLOCK - CRM_TMR3_PERIPH_CLOCK
* - CRM_TMR6_PERIPH_CLOCK - CRM_TMR14_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK - CRM_SPI2_PERIPH_CLOCK
* - CRM_USART2_PERIPH_CLOCK - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
{
/* enable periph clock */
if(TRUE == new_state)
{
CRM_REG(value) |= CRM_REG_BIT(value);
}
/* disable periph clock */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral reset
* @param value
* this parameter can be one of the following values:
* - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET - CRM_GPIOC_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET
* - CRM_SCFG_PERIPH_RESET - CRM_CMP_PERIPH_RESET - CRM_EXINT_PERIPH_RESET - CRM_ADC1_PERIPH_RESET
* - CRM_TMR1_PERIPH_RESET - CRM_SPI1_PERIPH_RESET - CRM_USART1_PERIPH_RESET - CRM_TMR15_PERIPH_RESET
* - CRM_TMR16_PERIPH_RESET - CRM_TMR17_PERIPH_RESET - CRM_TMR3_PERIPH_RESET - CRM_TMR6_PERIPH_RESET
* - CRM_TMR14_PERIPH_RESET - CRM_WWDT_PERIPH_RESET - CRM_SPI2_PERIPH_RESET - CRM_USART2_PERIPH_RESET
* - CRM_I2C1_PERIPH_RESET - CRM_I2C2_PERIPH_RESET - CRM_PWC_PERIPH_RESET
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
{
/* enable periph reset */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable periph reset */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral clock in sleep mode
* @param value
* this parameter can be one of the following values:
* - CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE
* - CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state)
{
/* enable periph clock in sleep mode */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable perph clock in sleep mode */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the crm clock source
* @param source
* this parameter can be one of the following values:
* - CRM_CLOCK_SOURCE_HICK
* - CRM_CLOCK_SOURCE_HEXT
* - CRM_CLOCK_SOURCE_PLL
* - CRM_CLOCK_SOURCE_LEXT
* - CRM_CLOCK_SOURCE_LICK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
{
switch(source)
{
case CRM_CLOCK_SOURCE_HICK:
CRM->ctrl_bit.hicken = new_state;
break;
case CRM_CLOCK_SOURCE_HEXT:
CRM->ctrl_bit.hexten = new_state;
break;
case CRM_CLOCK_SOURCE_PLL:
CRM->ctrl_bit.pllen = new_state;
break;
case CRM_CLOCK_SOURCE_LEXT:
CRM->bpdc_bit.lexten = new_state;
break;
case CRM_CLOCK_SOURCE_LICK:
CRM->ctrlsts_bit.licken = new_state;
break;
default:
break;
}
}
/**
* @brief clear the crm reset flags
* @param flag
* this parameter can be one of the following values:
* reset flag:
* - CRM_NRST_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* - CRM_ALL_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval none
*/
void crm_flag_clear(uint32_t flag)
{
switch(flag)
{
case CRM_NRST_RESET_FLAG:
case CRM_POR_RESET_FLAG:
case CRM_SW_RESET_FLAG:
case CRM_WDT_RESET_FLAG:
case CRM_WWDT_RESET_FLAG:
case CRM_LOWPOWER_RESET_FLAG:
case CRM_ALL_RESET_FLAG:
CRM->ctrlsts_bit.rstfc = TRUE;
while(CRM->ctrlsts_bit.rstfc == TRUE);
break;
case CRM_LICK_READY_INT_FLAG:
CRM->clkint_bit.lickstblfc = TRUE;
break;
case CRM_LEXT_READY_INT_FLAG:
CRM->clkint_bit.lextstblfc = TRUE;
break;
case CRM_HICK_READY_INT_FLAG:
CRM->clkint_bit.hickstblfc = TRUE;
break;
case CRM_HEXT_READY_INT_FLAG:
CRM->clkint_bit.hextstblfc = TRUE;
break;
case CRM_PLL_READY_INT_FLAG:
CRM->clkint_bit.pllstblfc = TRUE;
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
CRM->clkint_bit.cfdfc = TRUE;
break;
default:
break;
}
}
/**
* @brief select ertc clock
* @param value
* this parameter can be one of the following values:
* - CRM_ERTC_CLOCK_LEXT
* - CRM_ERTC_CLOCK_LICK
* - CRM_ERTC_CLOCK_HEXT_DIV
* @retval none
*/
void crm_ertc_clock_select(crm_ertc_clock_type value)
{
CRM->bpdc_bit.ertcsel = value;
}
/**
* @brief enable or disable ertc
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_ertc_clock_enable(confirm_state new_state)
{
CRM->bpdc_bit.ertcen = new_state;
}
/**
* @brief set crm ahb division
* @param value
* this parameter can be one of the following values:
* - CRM_AHB_DIV_1
* - CRM_AHB_DIV_2
* - CRM_AHB_DIV_4
* - CRM_AHB_DIV_8
* - CRM_AHB_DIV_16
* - CRM_AHB_DIV_64
* - CRM_AHB_DIV_128
* - CRM_AHB_DIV_256
* - CRM_AHB_DIV_512
* @retval none
*/
void crm_ahb_div_set(crm_ahb_div_type value)
{
CRM->cfg_bit.ahbdiv = value;
}
/**
* @brief set crm apb1 division
* @note the maximum frequency of APB1/APB2 clock is 120 MHz
* @param value
* this parameter can be one of the following values:
* - CRM_APB1_DIV_1
* - CRM_APB1_DIV_2
* - CRM_APB1_DIV_4
* - CRM_APB1_DIV_8
* - CRM_APB1_DIV_16
* @retval none
*/
void crm_apb1_div_set(crm_apb1_div_type value)
{
CRM->cfg_bit.apb1div = value;
}
/**
* @brief set crm apb2 division
* @note the maximum frequency of APB1/APB2 clock is 120 MHz
* @param value
* this parameter can be one of the following values:
* - CRM_APB2_DIV_1
* - CRM_APB2_DIV_2
* - CRM_APB2_DIV_4
* - CRM_APB2_DIV_8
* - CRM_APB2_DIV_16
* @retval none
*/
void crm_apb2_div_set(crm_apb2_div_type value)
{
CRM->cfg_bit.apb2div = value;
}
/**
* @brief set crm adc division
* @param value
* this parameter can be one of the following values:
* - CRM_ADC_DIV_2
* - CRM_ADC_DIV_4
* - CRM_ADC_DIV_6
* - CRM_ADC_DIV_8
* - CRM_ADC_DIV_12
* - CRM_ADC_DIV_16
* @retval none
*/
void crm_adc_clock_div_set(crm_adc_div_type div_value)
{
CRM->cfg_bit.adcdiv_l = div_value & 0x03;
CRM->cfg_bit.adcdiv_h = (div_value >> 2) & 0x01;
}
/**
* @brief enable or disable clock failure detection
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_failure_detection_enable(confirm_state new_state)
{
CRM->ctrl_bit.cfden = new_state;
}
/**
* @brief battery powered domain software reset
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_battery_powered_domain_reset(confirm_state new_state)
{
CRM->bpdc_bit.bpdrst = new_state;
}
/**
* @brief config crm pll
* @param clock_source
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* - CRM_PLL_SOURCE_HEXT_DIV
* @param mult_value (CRM_PLL_MULT_2~64)
* @retval none
*/
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value)
{
uint32_t pllrcfreq = 0;
crm_pll_fref_type pllfref = CRM_PLL_FREF_4M;
/* config pll clock source */
if(clock_source == CRM_PLL_SOURCE_HICK)
{
CRM->cfg_bit.pllrcs = FALSE;
pllrcfreq = (HICK_VALUE / 2);
CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
}
else
{
CRM->cfg_bit.pllrcs = TRUE;
if(CRM_PLL_SOURCE_HEXT == clock_source)
{
pllrcfreq = HEXT_VALUE;
CRM->cfg_bit.pllhextdiv = FALSE;
}
else
{
pllrcfreq = (HEXT_VALUE / 2);
CRM->cfg_bit.pllhextdiv = TRUE;
}
}
if((pllrcfreq > 3900000U) && (pllrcfreq < 5000000U))
{
pllfref = CRM_PLL_FREF_4M;
}
else if((pllrcfreq > 5200000U) && (pllrcfreq < 6250000U))
{
pllfref = CRM_PLL_FREF_6M;
}
else if((pllrcfreq > 7812500U) && (pllrcfreq < 8330000U))
{
pllfref = CRM_PLL_FREF_8M;
}
else if((pllrcfreq > 8330000U) && (pllrcfreq < 12500000U))
{
pllfref = CRM_PLL_FREF_12M;
}
else if((pllrcfreq > 15625000U) && (pllrcfreq < 20830000U))
{
pllfref = CRM_PLL_FREF_16M;
}
else if((pllrcfreq > 20830000U) && (pllrcfreq < 31255000U))
{
pllfref = CRM_PLL_FREF_25M;
}
/* config pll multiplication factor */
CRM->cfg_bit.pllmult_l = (mult_value & 0x0F);
CRM->cfg_bit.pllmult_h = ((mult_value & 0x30) >> 4);
/* config pll fref */
CRM->pll_bit.pllfref = pllfref;
}
/**
* @brief config crm pll function2, another method.
* pll_rcs_freq * pll_ns
* pll clock = --------------------------------
* pll_ms * pll_fr_n
* attemtion:
* 31 <= pll_ns <= 500
* 1 <= pll_ms <= 15
*
* pll_rcs_freq
* 2mhz <= ---------------------- <= 16mhz
* pll_ms
*
* pll_rcs_freq * pll_ns
* 500mhz <= -------------------------------- <= 1000mhz
* pll_ms
* @param clock_source
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* - CRM_PLL_SOURCE_HEXT_DIV
* @param pll_ns (31~500)
* @param pll_ms (1~15)
* @param pll_fr
* this parameter can be one of the following values:
* - CRM_PLL_FR_1
* - CRM_PLL_FR_2
* - CRM_PLL_FR_4
* - CRM_PLL_FR_8
* - CRM_PLL_FR_16
* - CRM_PLL_FR_32
* @retval none
*/
void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
uint16_t pll_ms, crm_pll_fr_type pll_fr)
{
/* config pll clock source */
if(clock_source == CRM_PLL_SOURCE_HICK)
{
CRM->cfg_bit.pllrcs = FALSE;
CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
}
else
{
CRM->cfg_bit.pllrcs = TRUE;
if(clock_source == CRM_PLL_SOURCE_HEXT)
{
CRM->cfg_bit.pllhextdiv = FALSE;
}
else
{
CRM->cfg_bit.pllhextdiv = TRUE;
}
}
/* config pll multiplication factor */
CRM->pll_bit.pllns = pll_ns;
CRM->pll_bit.pllms = pll_ms;
CRM->pll_bit.pllfr = pll_fr;
CRM->pll_bit.pllcfgen = TRUE;
}
/**
* @brief select system clock source
* @param value
* this parameter can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
* @retval none
*/
void crm_sysclk_switch(crm_sclk_type value)
{
CRM->cfg_bit.sclksel = value;
DUMMY_NOP();
}
/**
* @brief indicate which clock source is used as system clock
* @param none
* @retval crm_sclk
* this return can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
*/
crm_sclk_type crm_sysclk_switch_status_get(void)
{
return (crm_sclk_type)CRM->cfg_bit.sclksts;
}
/**
* @brief get crm clocks freqency
* @param clocks
* - pointer to the crm_clocks_freq structure
* @retval none
*/
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
{
uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
uint32_t pllrcsfreq = 0, pll_ms = 0, pll_ns = 0, pll_fr = 0;
crm_sclk_type sclk_source;
static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t adc_div_table[8] = {2, 4, 6, 8, 2, 12, 8, 16};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
case CRM_SCLK_HICK:
if(((CRM->misc2_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
clocks_struct->sclk_freq = HICK_VALUE * 6;
else
clocks_struct->sclk_freq = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
clocks_struct->sclk_freq = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
pll_clock_source = CRM->cfg_bit.pllrcs;
if(CRM->pll_bit.pllcfgen == FALSE)
{
/* get multiplication factor */
pll_mult = CRM->cfg_bit.pllmult_l;
pll_mult_h = CRM->cfg_bit.pllmult_h;
/* process high bits */
if((pll_mult_h != 0U) || (pll_mult == 15U))
{
pll_mult += ((16U * pll_mult_h) + 1U);
}
else
{
pll_mult += 2U;
}
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
clocks_struct->sclk_freq = (HICK_VALUE >> 1) * pll_mult;
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
clocks_struct->sclk_freq = (HEXT_VALUE / 2) * pll_mult;
}
else
{
clocks_struct->sclk_freq = HEXT_VALUE * pll_mult;
}
}
}
else
{
pll_ms = CRM->pll_bit.pllms;
pll_ns = CRM->pll_bit.pllns;
pll_fr = CRM->pll_bit.pllfr;
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
pllrcsfreq = (HICK_VALUE >> 1);
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
pllrcsfreq = (HEXT_VALUE / 2);
}
else
{
pllrcsfreq = HEXT_VALUE;
}
}
clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr)));
}
break;
default:
clocks_struct->sclk_freq = HICK_VALUE;
break;
}
/* compute sclk, ahbclk, abp1clk apb2clk and adcclk frequencies */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sclk_ahb_div_table[temp];
/* ahbclk frequency */
clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
/* get apb1 division */
temp = CRM->cfg_bit.apb1div;
div_value = ahb_apb1_div_table[temp];
/* apb1clk frequency */
clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
/* get apb2 division */
temp = CRM->cfg_bit.apb2div;
div_value = ahb_apb2_div_table[temp];
/* apb2clk frequency */
clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
/* get adc division */
temp = CRM->cfg_bit.adcdiv_h;
temp = ((temp << 2) | (CRM->cfg_bit.adcdiv_l));
div_value = adc_div_table[temp];
/* adcclk clock frequency */
clocks_struct->adc_freq = clocks_struct->apb2_freq / div_value;
}
/**
* @brief set crm clkout
* @param clkout
* this parameter can be one of the following values:
* - CRM_CLKOUT_NOCLK
* - CRM_CLKOUT_LICK
* - CRM_CLKOUT_LEXT
* - CRM_CLKOUT_SCLK
* - CRM_CLKOUT_HICK
* - CRM_CLKOUT_HEXT
* - CRM_CLKOUT_PLL_DIV_2
* - CRM_CLKOUT_PLL_DIV_4
* - CRM_CLKOUT_ADC
* @retval none
*/
void crm_clock_out_set(crm_clkout_select_type clkout)
{
CRM->cfg_bit.clkout_sel = clkout & 0x7;
CRM->misc1_bit.clkout_sel = (clkout >> 3) & 0x1;
}
/**
* @brief config crm interrupt
* @param int
* this parameter can be any combination of the following values:
* - CRM_LICK_STABLE_INT
* - CRM_LEXT_STABLE_INT
* - CRM_HICK_STABLE_INT
* - CRM_HEXT_STABLE_INT
* - CRM_PLL_STABLE_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
{
if(new_state == TRUE)
CRM->clkint |= crm_int;
else
CRM->clkint &= ~crm_int;
}
/**
* @brief auto step clock switch enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_auto_step_mode_enable(confirm_state new_state)
{
if(new_state == TRUE)
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
else
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
/**
* @brief config hick divider select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK48_DIV6
* - CRM_HICK48_NODIV
* @retval none
*/
void crm_hick_divider_select(crm_hick_div_6_type value)
{
CRM->misc1_bit.hickdiv = value;
}
/**
* @brief hick as system clock frequency select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK_SCLK_8MHZ
* - CRM_HICK_SCLK_48MHZ
* @retval none
*/
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
{
crm_hick_divider_select(CRM_HICK48_NODIV);
CRM->misc2_bit.hick_to_sclk = value;
}
/**
* @brief set crm clkout division
* @param clkout_div
* this parameter can be one of the following values:
* - CRM_CLKOUT_DIV_1
* - CRM_CLKOUT_DIV_2
* - CRM_CLKOUT_DIV_4
* - CRM_CLKOUT_DIV_8
* - CRM_CLKOUT_DIV_16
* - CRM_CLKOUT_DIV_64
* - CRM_CLKOUT_DIV_128
* - CRM_CLKOUT_DIV_256
* - CRM_CLKOUT_DIV_512
* @retval none
*/
void crm_clkout_div_set(crm_clkout_div_type clkout_div)
{
CRM->misc1_bit.clkoutdiv = clkout_div;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_debug.c
* @brief contains all the functions for the debug firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup DEBUG
* @brief DEBUG driver modules
* @{
*/
#ifdef DEBUG_MODULE_ENABLED
/** @defgroup DEBUG_private_functions
* @{
*/
/**
* @brief get debug device id
* @param none
* @retval the debug device id
*/
uint16_t debug_device_id_get(void)
{
return (uint16_t)DEBUGMCU->pid;
}
/**
* @brief set periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_SLEEP
* - DEBUG_DEEPSLEEP
* - DEBUG_STANDBY
* - DEBUG_WDT_PAUSE
* - DEBUG_WWDT_PAUSE
* - DEBUG_TMR1_PAUSE
* - DEBUG_TMR3_PAUSE
* - DEBUG_ERTC_PAUSE
* - DEBUG_I2C1_SMBUS_TIMEOUT
* - DEBUG_I2C2_SMBUS_TIMEOUT
* - DEBUG_TMR6_PAUSE
* - DEBUG_ERTC_512_PAUSE
* - DEBUG_TMR15_PAUSE
* - DEBUG_TMR16_PAUSE
* - DEBUG_TMR17_PAUSE
* - DEBUG_TMR14_PAUSE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUGMCU->ctrl |= periph_debug_mode;
}
else
{
DEBUGMCU->ctrl &= ~periph_debug_mode;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_dma.c
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
#ifdef DMA_MODULE_ENABLED
/** @defgroup DMA_private_functions
* @{
*/
/**
* @brief reset the dmax channely registers.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @retval none
*/
void dma_reset(dma_channel_type* dmax_channely)
{
uint32_t temp = 0;
dmax_channely->ctrl_bit.chen = FALSE;
dmax_channely->ctrl = 0;
dmax_channely->dtcnt = 0;
dmax_channely->paddr = 0;
dmax_channely->maddr = 0;
temp = (uint32_t)dmax_channely;
/* dma1 channel */
DMA1->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
}
/**
* @brief set the number of data to be transferred
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param data_number: the number of data to be transferred(0x0000~0xFFFF)
* transfer.
* @retval none.
*/
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number)
{
dmax_channely->dtcnt = data_number;
}
/**
* @brief get number of data from dtcnt register
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @retval the number of data.
*/
uint16_t dma_data_number_get(dma_channel_type* dmax_channely)
{
return (uint16_t)dmax_channely->dtcnt;
}
/**
* @brief enable or disable dma interrupt
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param dma_int:
* this parameter can be any combination of the following values:
* - DMA_FDT_INT
* - DMA_HDT_INT
* - DMA_DTERR_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state)
{
if (new_state != FALSE)
{
dmax_channely->ctrl |= dma_int;
}
else
{
dmax_channely->ctrl &= ~dma_int;
}
}
/**
* @brief enable or disable dma channely
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param new_state (TRUE or FALSE)
* @retval None
*/
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state)
{
dmax_channely->ctrl_bit.chen = new_state;
}
/**
* @brief get dma interrupt flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval state of dma flag
*/
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
temp = DMA1->sts;
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval state of dma flag
*/
flag_status dma_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
temp = DMA1->sts;
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief clear dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval none
*/
void dma_flag_clear(uint32_t dmax_flag)
{
DMA1->clr = dmax_flag;
}
/**
* @brief dma init config with its default value.
* @param dma_init_struct : pointer to a dma_init_type structure which will
* be initialized.
* @retval none
*/
void dma_default_para_init(dma_init_type* dma_init_struct)
{
dma_init_struct->peripheral_base_addr = 0x0;
dma_init_struct->memory_base_addr = 0x0;
dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct->buffer_size = 0x0;
dma_init_struct->peripheral_inc_enable = FALSE;
dma_init_struct->memory_inc_enable = FALSE;
dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct->loop_mode_enable = FALSE;
dma_init_struct->priority = DMA_PRIORITY_LOW;
}
/**
* @brief dma init
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param dma_initstruct : pointer to a dma_init_type structure.
* @retval none
*/
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct)
{
/* clear ctrl register dtd bit and m2m bit */
dmax_channely->ctrl &= 0xbfef;
dmax_channely->ctrl |= dma_init_struct->direction;
dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
dmax_channely->dtcnt = dma_init_struct->buffer_size;
dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
dmax_channely->maddr = dma_init_struct->memory_base_addr;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_exint.c
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup EXINT
* @brief EXINT driver modules
* @{
*/
#ifdef EXINT_MODULE_ENABLED
/** @defgroup EXINT_private_functions
* @{
*/
/**
* @brief exint reset
* @param none
* @retval none
*/
void exint_reset(void)
{
EXINT->inten = 0x00000000;
EXINT->polcfg1 = 0x00000000;
EXINT->polcfg2 = 0x00000000;
EXINT->evten = 0x00000000;
EXINT->intsts = 0x003FFFFF;
}
/**
* @brief exint default para init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_default_para_init(exint_init_type *exint_struct)
{
exint_struct->line_enable = FALSE;
exint_struct->line_select = EXINT_LINE_NONE;
exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
exint_struct->line_mode = EXINT_LINE_EVENT;
}
/**
* @brief exint init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_init(exint_init_type *exint_struct)
{
uint32_t line_index = 0;
line_index = exint_struct->line_select;
EXINT->inten &= ~line_index;
EXINT->evten &= ~line_index;
if(exint_struct->line_enable != FALSE)
{
if(exint_struct->line_mode == EXINT_LINE_INTERRUPT)
{
EXINT->inten |= line_index;
}
else
{
EXINT->evten |= line_index;
}
EXINT->polcfg1 &= ~line_index;
EXINT->polcfg2 &= ~line_index;
if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
{
EXINT->polcfg1 |= line_index;
}
else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
{
EXINT->polcfg2 |= line_index;
}
else
{
EXINT->polcfg1 |= line_index;
EXINT->polcfg2 |= line_index;
}
}
}
/**
* @brief clear exint flag
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval none
*/
void exint_flag_clear(uint32_t exint_line)
{
EXINT->intsts = exint_line;
}
/**
* @brief get exint flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval state of exint flag
*/
flag_status exint_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get exint interrupt flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval state of exint flag
*/
flag_status exint_interrupt_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line;
exint_flag = exint_flag & EXINT->inten;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief generate exint software interrupt event
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval none
*/
void exint_software_interrupt_event_generate(uint32_t exint_line)
{
EXINT->swtrg |= exint_line;
}
/**
* @brief enable or disable exint interrupt
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @param new_state (TRUE or FALSE)
* @retval none
*/
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->inten |= exint_line;
}
else
{
EXINT->inten &= ~exint_line;
}
}
/**
* @brief enable or disable exint event
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @param new_state (TRUE or FALSE)
* @retval none
*/
void exint_event_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->evten |= exint_line;
}
else
{
EXINT->evten &= ~exint_line;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_flash.c
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup FLASH
* @brief FLASH driver modules
* @{
*/
#ifdef FLASH_MODULE_ENABLED
/** @defgroup FLASH_private_functions
* @{
*/
/**
* @brief check whether the specified flash flag is set or not.
* @param flash_flag: specifies the flash flag to check.
* this parameter can be one of flash flag status:
* - FLASH_OBF_FLAG
* - FLASH_ODF_FLAG
* - FLASH_PRGMERR_FLAG
* - FLASH_EPPERR_FLAG
* - FLASH_USDERR_FLAG
* @retval the new state of flash_flag (SET or RESET).
*/
flag_status flash_flag_get(uint32_t flash_flag)
{
flag_status status = RESET;
uint32_t flag_position;
flag_position = flash_flag & 0x70000000;
flash_flag &= 0x8FFFFFFF;
switch(flag_position)
{
case 0x00000000:
if(FLASH->sts & flash_flag)
status = SET;
break;
case 0x40000000:
if(FLASH->usd & flash_flag)
status = SET;
break;
default:
break;
}
/* return the new state of flash_flag (SET or RESET) */
return status;
}
/**
* @brief clear the flash flag.
* @param flash_flag: specifies the flash flags to clear.
* this parameter can be any combination of the following values:
* - FLASH_ODF_FLAG
* - FLASH_PRGMERR_FLAG
* - FLASH_EPPERR_FLAG
* @retval none
*/
void flash_flag_clear(uint32_t flash_flag)
{
FLASH->sts = flash_flag;
}
/**
* @brief return the flash operation status.
* @param none
* @retval status: the returned value can be: FLASH_OPERATE_BUSY,
* FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
*/
flash_status_type flash_operation_status_get(void)
{
flash_status_type flash_status = FLASH_OPERATE_DONE;
if(FLASH->sts_bit.obf != RESET)
{
flash_status = FLASH_OPERATE_BUSY;
}
else if(FLASH->sts_bit.prgmerr != RESET)
{
flash_status = FLASH_PROGRAM_ERROR;
}
else if(FLASH->sts_bit.epperr != RESET)
{
flash_status = FLASH_EPP_ERROR;
}
else
{
flash_status = FLASH_OPERATE_DONE;
}
/* return the flash status */
return flash_status;
}
/**
* @brief wait for flash operation complete or timeout.
* @param time_out: flash operation timeout
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_operation_wait_for(uint32_t time_out)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* check for the flash status */
status = flash_operation_status_get();
while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
{
status = flash_operation_status_get();
time_out--;
}
if(time_out == 0x00)
{
status = FLASH_OPERATE_TIMEOUT;
}
/* return the status */
return status;
}
/**
* @brief unlock the flash controller.
* @param none
* @retval none
*/
void flash_unlock(void)
{
FLASH->unlock = FLASH_UNLOCK_KEY1;
FLASH->unlock = FLASH_UNLOCK_KEY2;
}
/**
* @brief lock the flash controller.
* @param none
* @retval none
*/
void flash_lock(void)
{
FLASH->ctrl_bit.oplk = TRUE;
}
/**
* @brief erase a specified flash sector.
* @param sector_address: the sector address to be erased.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_sector_erase(uint32_t sector_address)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.secers = TRUE;
FLASH->addr = sector_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the secers bit */
FLASH->ctrl_bit.secers = FALSE;
/* return the erase status */
return status;
}
/**
* @brief erase flash all internal sectors.
* @param none
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_internal_all_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
/* return the erase status */
return status;
}
/**
* @brief erase the flash user system data.
* @note this functions erases all user system data except the fap byte.
* when fap high level enabled, can't use this function.
* @param none
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_user_system_data_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
uint16_t fap_val = FAP_RELIEVE_KEY;
/* get the flash access protection status */
if(flash_fap_status_get() != RESET)
{
fap_val = 0x0000;
}
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* erase the user system data */
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the last flash access protection value */
USD->fap = (uint16_t)fap_val;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the erase status */
return status;
}
/**
* @brief program a word at a specified address.
* @param address: specifies the address to be programmed, word alignment is recommended.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_word_program(uint32_t address, uint32_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a halfword at a specified address.
* @param address: specifies the address to be programmed, halfword alignment is recommended.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a byte at a specified address.
* @param address: specifies the address to be programmed.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_byte_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a halfword at a specified user system data address.
* @param address: specifies the address to be programmed.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the user system data program status */
return status;
}
/**
* @brief config erase/program protection for the desired sectors.
* @param sector_bits(1:ENABLE, 0:DISABLE)
* the pointer of the address of the sectors to be erase/program protected.
* the first 16bits general every bit is used to protect the 4KB bytes. the
* bit 31 is used to protect the extension memory.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_epp_set(uint32_t *sector_bits)
{
uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
flash_status_type status = FLASH_OPERATE_DONE;
sector_bits[0] = (uint32_t)(~sector_bits[0]);
epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usdprgm = TRUE;
USD->epp0 = epp_data[0];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
USD->epp1 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp2 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp3 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the erase/program protection operation status */
return status;
}
/**
* @brief return the flash erase/program protection status.
* @param sector_bits: pointer to get the epps register.
* @retval none
*/
void flash_epp_status_get(uint32_t *sector_bits)
{
/* return the flash erase/program protection register value */
sector_bits[0] = (uint32_t)(FLASH->epps);
}
/**
* @brief enable or disable the flash access protection.
* @note if the user has already programmed the other user system data before calling
* this function, must re-program them since this function erase all user system data.
* @param new_state: new state of the flash access protection.
* this parameter can be: TRUE or FALSE.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_fap_enable(confirm_state new_state)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
if(new_state == FALSE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_RELIEVE_KEY;
/* Wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
/* return the flash access protection operation status */
return status;
}
/**
* @brief check the flash access protection status.
* @param none
* @retval flash access protection status(SET or RESET)
*/
flag_status flash_fap_status_get(void)
{
return (flag_status)FLASH->usd_bit.fap;
}
/**
* @brief enable or disable the flash access protection high level.
* @note if the user has already programmed the other user system data before calling
* this function, must re-program them since this function erase all user system data.
* @param new_state: new state of the flash access protection high level.
* this parameter can be: TRUE or FALSE.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_fap_high_level_enable(confirm_state new_state)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
if(new_state == FALSE)
{
FLASH->ctrl_bit.fap_hl_dis = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_RELIEVE_KEY;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
else
{
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_HIGH_LEVEL_KEY;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
/* return the flash access protection operation status */
return status;
}
/**
* @brief check the flash access protection high level status.
* @param none
* @retval flash access protection high level status(SET or RESET)
*/
flag_status flash_fap_high_level_status_get(void)
{
return (flag_status)FLASH->usd_bit.fap_hl;
}
/**
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1.
* @param usd_ssb: the system setting byte
* @note this parameter usd_ssb must contain a combination of all the following 4 types of data
* type 1: wdt_ato_en, select the wdt auto start
* this data can be one of the following values:
* - USD_WDT_ATO_DISABLE: disable wdt auto start
* - USD_WDT_ATO_ENABLE: enable wdt auto start
* type 2: depslp_rst, reset event when entering deepsleep mode.
* this data can be one of the following values:
* - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
* - USD_DEPSLP_RST: reset generated when entering in deepsleep
* type 3: stdby_rst, reset event when entering standby mode.
* this data can be one of the following values:
* - USD_STDBY_NO_RST: no reset generated when entering in standby
* - USD_STDBY_RST: reset generated when entering in standby
* type 4: boot1, at startup, when boot0 pin is high level, selected the device boot from bootmem/sram.
* this data can be one of the following values:
* - USD_BOOT1_LOW: when boot0 is high level, boot from bootmem
* - USD_BOOT1_HIGH: when boot0 is high level, boot from sram
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_ssb_set(uint8_t usd_ssb)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->ssb = usd_ssb;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the user system data program status */
return status;
}
/**
* @brief return the flash system setting byte status.
* @param none
* @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
* stdby_rst(bit2) and boot1(bit4).
*/
uint8_t flash_ssb_status_get(void)
{
/* return the system setting byte status */
return (uint8_t)(FLASH->usd >> 2);
}
/**
* @brief enable or disable the specified flash interrupts.
* @param flash_int: specifies the flash interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - FLASH_ERR_INT
* - FLASH_ODF_INT
* @param new_state: new state of the specified flash interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
{
if(flash_int & FLASH_ERR_INT)
FLASH->ctrl_bit.errie = new_state;
if(flash_int & FLASH_ODF_INT)
FLASH->ctrl_bit.odfie = new_state;
}
/**
* @brief enable main block security library function.
* @param pwd: slib password
* start_sector: security library start sector
* inst_start_sector: security library i-bus area start sector
* end_sector: security library end sector
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector)
{
uint32_t slib_range;
flash_status_type status = FLASH_OPERATE_DONE;
/*check range param limits*/
if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \
(inst_start_sector != 0x7FF)) || (start_sector > end_sector))
return FLASH_PROGRAM_ERROR;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
slib_range = ((uint32_t)(inst_start_sector << 11) & FLASH_SLIB_INST_START_SECTOR) | \
((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \
(start_sector & FLASH_SLIB_START_SECTOR);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->slib_set_range = slib_range;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
return status;
}
/**
* @brief disable main block slib when slib enabled.
* @param pwd: slib password
* @retval success or error
*/
error_status flash_slib_disable(uint32_t pwd)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* write password to disable slib */
FLASH->slib_pwd_clr = pwd;
status = flash_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
return SUCCESS;
else
return ERROR;
}
return ERROR;
}
/**
* @brief get the main block slib state.
* @param none
* @retval SET or RESET
*/
flag_status flash_slib_state_get(void)
{
if(FLASH->slib_sts0_bit.slib_enf)
return SET;
else
return RESET;
}
/**
* @brief get the main block start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_start_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
}
/**
* @brief get the main block inst start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_inststart_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_inst_ss;
}
/**
* @brief get the main block end sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_end_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_es;
}
/**
* @brief flash crc calibration.
* @param start_addr: crc calibration start sector address
* sector_cnt: crc calibration sector count
* @retval uint32: crc calibration result
*/
uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt)
{
FLASH->crc_addr = start_addr;
FLASH->crc_ctrl = sector_cnt | 0x10000;
flash_operation_wait_for(OPERATION_TIMEOUT);
return FLASH->crc_chkr;
}
/**
* @brief enable boot memory as extension mode.
* @note this function is irreversible, can not disable!!!
* @param none
* @retval none.
*/
void flash_boot_memory_extension_mode_enable(void)
{
if(FLASH->slib_sts0_bit.btm_ap_enf == RESET)
{
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
FLASH->btm_mode_set = 0;
flash_operation_wait_for(OPERATION_TIMEOUT);
}
}
/**
* @brief enable extension memory security library function.
* @param pwd: slib password
* inst_start_sector: extension memory security library i-bus area start sector, range 0~3 or 0xFF
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t inst_start_sector)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->em_slib_set = (uint32_t)(inst_start_sector << 16) + (uint32_t)0x5AA5;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
return status;
}
/**
* @brief get the extension memory slib state.
* @param none
* @retval SET or RESET
*/
flag_status flash_extension_memory_slib_state_get(void)
{
if(FLASH->slib_sts0_bit.em_slib_enf)
return SET;
else
return RESET;
}
/**
* @brief get the extension memory inst start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_em_slib_inststart_sector_get(void)
{
return (uint16_t)FLASH->slib_sts0_bit.em_slib_inst_ss;
}
/**
* @brief config flash low power mode enable or disable.
* if enabled, when system entry deep sleep mode, flash also entry low power mode.
* @param new_state: new state of the flash low power mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void flash_low_power_mode_enable(confirm_state new_state)
{
FLASH->ctrl_bit.lpmen = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

493
vd960Loop/libraries/drivers/src/at32f421_gpio.c Normal file
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@@ -0,0 +1,493 @@
/**
**************************************************************************
* @file at32f421_gpio.c
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
#ifdef GPIO_MODULE_ENABLED
/** @defgroup GPIO_private_functions
* @{
*/
/**
* @brief reset the gpio register
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval none
*/
void gpio_reset(gpio_type *gpio_x)
{
if(gpio_x == GPIOA)
{
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOB)
{
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOC)
{
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOF)
{
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the gpio peripheral.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_init_struct: pointer to gpio init structure.
* @retval none
*/
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
{
uint16_t pinx_value, pin_index = 0;
pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
while(pinx_value > 0)
{
if(pinx_value & 0x01)
{
gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
}
pinx_value >>= 1;
pin_index++;
}
}
/**
* @brief fill each gpio_init_type member with its default value.
* @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
* @retval none
*/
void gpio_default_para_init(gpio_init_type *gpio_init_struct)
{
/* reset gpio init structure parameters values */
gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
}
/**
* @brief read the specified input port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if(pins != (pins & gpio_x->idt))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief read the specified gpio input data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
uint16_t gpio_input_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->idt));
}
/**
* @brief read the specified output port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if((gpio_x->odt & pins) != RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief read the specified gpio ouput data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
uint16_t gpio_output_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->odt));
}
/**
* @brief set the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->scr = pins;
}
/**
* @brief clear the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->clr = pins;
}
/**
* @brief set or clear the selected data port bit.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
* @retval none
*/
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
{
if(bit_state != FALSE)
{
gpio_x->scr = pins;
}
else
{
gpio_x->clr = pins;
}
}
/**
* @brief write data to the specified gpio data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param port_value: specifies the value to be written to the port output data register.
* @retval none
*/
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
{
gpio_x->odt = port_value;
}
/**
* @brief write protect gpio pins configuration registers.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be any combination of the following:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
{
uint32_t temp = 0x00010000;
temp |= pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* reset wpen bit */
gpio_x->wpr = pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* read wpen bit*/
temp = gpio_x->wpr;
/* read wpen bit*/
temp = gpio_x->wpr;
}
/**
* @brief enable or disable gpio pins huge driven.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param new_state: new state of the slew rate.
* this parameter can be: true or false.
* @retval none
*/
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
{
if(new_state != FALSE)
{
gpio_x->hdrv |= pins;
}
else
{
gpio_x->hdrv &= ~pins;
}
}
/**
* @brief configure the pin's muxing function.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_pin_source: specifies the pin for the muxing function.
* this parameter can be one of the following values:
* - GPIO_PINS_SOURCE0
* - GPIO_PINS_SOURCE1
* - GPIO_PINS_SOURCE2
* - GPIO_PINS_SOURCE3
* - GPIO_PINS_SOURCE4
* - GPIO_PINS_SOURCE5
* - GPIO_PINS_SOURCE6
* - GPIO_PINS_SOURCE7
* - GPIO_PINS_SOURCE8
* - GPIO_PINS_SOURCE9
* - GPIO_PINS_SOURCE10
* - GPIO_PINS_SOURCE11
* - GPIO_PINS_SOURCE12
* - GPIO_PINS_SOURCE13
* - GPIO_PINS_SOURCE14
* - GPIO_PINS_SOURCE15
* @param gpio_mux: select the pin to used as muxing function.
* this parameter can be one of the following values:
* - GPIO_MUX_0
* - GPIO_MUX_1
* - GPIO_MUX_2
* - GPIO_MUX_3
* - GPIO_MUX_4
* - GPIO_MUX_5
* - GPIO_MUX_6
* - GPIO_MUX_7
* @retval none
*/
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
if(gpio_pin_source >> 0x03)
{
gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxh | temp;
gpio_x->muxh = temp_2;
}
else
{
gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxl | temp;
gpio_x->muxl = temp_2;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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@@ -0,0 +1,730 @@
/**
**************************************************************************
* @file at32f421_i2c.c
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup I2C
* @brief I2C driver modules
* @{
*/
#ifdef I2C_MODULE_ENABLED
/** @defgroup I2C_private_functions
* @{
*/
/**
* @brief reset the i2c register
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none
*/
void i2c_reset(i2c_type *i2c_x)
{
if(i2c_x == I2C1)
{
crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
}
else if(i2c_x == I2C2)
{
crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
}
}
/**
* @brief software reset.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.reset = new_state;
}
/**
* @brief init i2c speed and duty cycle.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param duty
* this parameter can be one of the following values:
* - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
* - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
* @param speed: i2c scl clock speed, such as 100000
* @retval none
*/
void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed)
{
uint32_t apb_freq = 0;
uint16_t freq_mhz = 0, temp = 0;
crm_clocks_freq_type clocks;
/* disable i2c peripherals */
i2c_x->ctrl1_bit.i2cen = FALSE;
/* get system clock */
crm_clocks_freq_get(&clocks);
if((i2c_x == I2C1) || (i2c_x == I2C2))
{
apb_freq = clocks.apb1_freq;
}
freq_mhz = (apb_freq / 1000000);
/* set i2c input clock frequency */
i2c_x->ctrl2_bit.clkfreq = freq_mhz;
/* standard mode */
if(speed <= 100000)
{
temp = (uint16_t)(apb_freq / (speed << 1));
if (temp < 0x04)
{
temp = 0x04;
}
/* set scl clock */
i2c_x->clkctrl_bit.speed = temp;
/* disable fast mode */
i2c_x->clkctrl_bit.speedmode = FALSE;
/* set the maximum rise time */
if((freq_mhz + 1) > 0x3F)
{
i2c_x->tmrise_bit.risetime = 0x3F;
}
else
{
i2c_x->tmrise_bit.risetime = (freq_mhz + 1);
}
}
/* fast mode */
else
{
if (duty == I2C_FSMODE_DUTY_2_1)
{
temp = (uint16_t)(apb_freq / (speed * 3));
/* the ratio of high level to low level is 1:2 */
i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_2_1;
}
else
{
temp = (uint16_t)(apb_freq / (speed * 25));
/* the ratio of high level to low level is 9:16 */
i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_16_9;
}
if (temp == 0)
{
temp = 0x0001;
}
/* set scl clock*/
i2c_x->clkctrl_bit.speed = temp;
/* set the mode to fast mode */
i2c_x->clkctrl_bit.speedmode = TRUE;
/* set the maximum rise time */
if(speed <= 400000)
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
else
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)120) / (uint16_t)1000) + (uint16_t)1);
}
}
}
/**
* @brief config own address1.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param mode
* this parameter can be one of the following values:
* - I2C_ADDRESS_MODE_7BIT: 7bit address.
* - I2C_ADDRESS_MODE_10BIT: 10bit address.
* @param address: own address1, such as 0xb0.
* @retval none
*/
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
{
/* set address mode */
i2c_x->oaddr1_bit.addr1mode = mode;
/* set own address1 */
i2c_x->oaddr1_bit.addr1 = address;
}
/**
* @brief config own address2.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: specifies the 7bit i2c own address2, such as 0xa0.
* @retval none.
*/
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address)
{
i2c_x->oaddr2_bit.addr2 = (address >> 1);
}
/**
* @brief enable or disable own address2.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->oaddr2_bit.addr2en = new_state;
}
/**
* @brief enable or disable the smbus mode
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.permode = new_state;
}
/**
* @brief enable or disable i2c periph
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.i2cen = new_state;
}
/**
* @brief config fast mode duty cycle
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param duty
* this parameter can be one of the following values:
* - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
* - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
* @retval none
*/
void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty)
{
i2c_x->clkctrl_bit.dutymode = duty;
}
/**
* @brief enable or disable clock stretch.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.stretch = !new_state;
}
/**
* @brief enable or disable acknowledge.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none.
*/
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.acken = new_state;
}
/**
* @brief master receiving mode acknowledge control.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param pos
* this parameter can be one of the following values:
* - I2C_MASTER_ACK_CURRENT: acken bit acts on the current byte
* - I2C_MASTER_ACK_NEXT: acken bit acts on the next byte
* @retval none
*/
void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos)
{
i2c_x->ctrl1_bit.mackctrl = pos;
}
/**
* @brief pec position set.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param pos
* this parameter can be one of the following values:
* - I2C_PEC_POSITION_CURRENT: the current byte is pec
* - I2C_PEC_POSITION_NEXT: the next byte is pec
* @retval none
*/
void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos)
{
i2c_x->ctrl1_bit.mackctrl = pos;
}
/**
* @brief enable or disable general call.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.gcaen = new_state;
}
/**
* @brief enable or disable arp mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.arpen = new_state;
}
/**
* @brief config smbus host or device.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
* this parameter can be one of the following values:
* - I2C_SMBUS_MODE_DEVICE: smbus device.
* - I2C_SMBUS_MODE_HOST: smbus host.
* @retval none
*/
void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode)
{
i2c_x->ctrl1_bit.smbmode = mode;
}
/**
* @brief drive the smbus alert pin high or low.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
* this parameter can be one of the following values:
* - I2C_SMBUS_ALERT_LOW: smbus alert pin set low.
* - I2C_SMBUS_ALERT_HIGH: smbus alert pin set high.
* @retval none
*/
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
{
i2c_x->ctrl1_bit.smbalert = level;
}
/**
* @brief enable or disable pec transfer.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.pecten = new_state;
}
/**
* @brief enable or disable pec calcultetion.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.pecen = new_state;
}
/**
* @brief get pec value.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval uint8_t: pec value.
*/
uint8_t i2c_pec_value_get(i2c_type *i2c_x)
{
return i2c_x->sts2_bit.pecval;
}
/**
* @brief enable or disable if the next dma transfer will be the last one.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.dmaend = new_state;
}
/**
* @brief enable or disable dma requests.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.dmaen = new_state;
}
/**
* @brief enable or disable interrupt
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param source
* this parameter can be one of the following values:
* - I2C_DATA_INT: data interrupt.
* - I2C_EV_INT: event interrupt.
* - I2C_ERR_INT: error interrupt.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state)
{
if (new_state != FALSE)
{
i2c_x->ctrl2 |= source;
}
else
{
i2c_x->ctrl2 &= (uint16_t)~source;
}
}
/**
* @brief generate start condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none.
*/
void i2c_start_generate(i2c_type *i2c_x)
{
i2c_x->ctrl1_bit.genstart = TRUE;
}
/**
* @brief generate stop condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none.
*/
void i2c_stop_generate(i2c_type *i2c_x)
{
i2c_x->ctrl1_bit.genstop = TRUE;
}
/**
* @brief transmit the slave address.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: specifies the slave address which will be transmitted
* @param direction
* this parameter can be one of the following values:
* - I2C_DIRECTION_TRANSMIT: transmit mode.
* - I2C_DIRECTION_RECEIVE: receive mode.
* @retval none.
*/
void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction)
{
if(direction == I2C_DIRECTION_TRANSMIT)
{
i2c_x->dt = address & 0xFE;
}
else
{
i2c_x->dt = address | 0x01;
}
}
/**
* @brief send a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param data: byte to be transmitted.
* @retval none
*/
void i2c_data_send(i2c_type *i2c_x, uint8_t data)
{
i2c_x->dt = data;
}
/**
* @brief receive a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval uint8_t: received byte
*/
uint8_t i2c_data_receive(i2c_type *i2c_x)
{
return (uint8_t)i2c_x->dt;
}
/**
* @brief get flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param flag
* this parameter can be one of the following values:
* - I2C_STARTF_FLAG: start condition generation complete flag.
* - I2C_ADDR7F_FLAG: 0~7 bit address match flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_TRMODE_FLAG: transmission mode.
* - I2C_BUSYF_FLAG: bus busy flag transmission mode.
* - I2C_DIRF_FLAG: transmission direction flag.
* - I2C_GCADDRF_FLAG: general call address received flag.
* - I2C_DEVADDRF_FLAG: smbus device address received flag.
* - I2C_HOSTADDRF_FLAG: smbus host address received flag.
* - I2C_ADDR2_FLAG: own address 2 received flag.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t reg = 0, value = 0;
reg = flag >> 28;
flag &= (uint32_t)0x00FFFFFF;
if(reg == 0)
{
value = i2c_x->sts1;
}
else
{
flag = (uint32_t)(flag >> 16);
value = i2c_x->sts2;
}
if((value & flag) != (uint32_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief get interrupt flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param flag
* this parameter can be one of the following values:
* - I2C_STARTF_FLAG: start condition generation complete flag.
* - I2C_ADDR7F_FLAG: 0~7 bit address match flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t reg = 0, value = 0, iten = 0;
switch(flag)
{
case I2C_STARTF_FLAG:
case I2C_ADDR7F_FLAG:
case I2C_TDC_FLAG:
case I2C_ADDRHF_FLAG:
case I2C_STOPF_FLAG:
iten = i2c_x->ctrl2_bit.evtien;
break;
case I2C_RDBF_FLAG:
case I2C_TDBE_FLAG:
iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien;
break;
case I2C_BUSERR_FLAG:
case I2C_ARLOST_FLAG:
case I2C_ACKFAIL_FLAG:
case I2C_OUF_FLAG:
case I2C_PECERR_FLAG:
case I2C_TMOUT_FLAG:
case I2C_ALERTF_FLAG:
iten = i2c_x->ctrl2_bit.errien;
break;
default:
break;
}
reg = flag >> 28;
flag &= (uint32_t)0x00FFFFFF;
if(reg == 0)
{
value = i2c_x->sts1;
}
else
{
flag = (uint32_t)(flag >> 16);
value = i2c_x->sts2;
}
if(((value & flag) != (uint32_t)RESET) && (iten))
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param flag
* this parameter can be any combination of the following values:
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag.
* @retval none
*/
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
{
i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
if(flag & I2C_ADDR7F_FLAG)
{
UNUSED(i2c_x->sts1);
UNUSED(i2c_x->sts2);
}
if(flag & I2C_STOPF_FLAG)
{
UNUSED(i2c_x->sts1);
i2c_x->ctrl1_bit.i2cen = TRUE;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_misc.c
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
#ifdef MISC_MODULE_ENABLED
/** @defgroup MISC_private_functions
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @brief system reset
* @param none
* @retval none
*/
void nvic_system_reset(void)
{
NVIC_SystemReset();
}
/**
* @brief enable nvic irq
* @param irqn (IRQn_Type number)
* @param preempt_priority: preemptive priority value (starting from 0)
* @param sub_priority: subpriority value (starting from 0)
* @retval none
*/
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
{
uint32_t temp_priority = 0;
/* encode priority */
temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
/* set priority */
NVIC_SetPriority(irqn, temp_priority);
/* enable irqn */
NVIC_EnableIRQ(irqn);
}
/**
* @brief disable nvic irq number
* @param irqn (IRQn_Type number)
* @retval none
*/
void nvic_irq_disable(IRQn_Type irqn)
{
NVIC_DisableIRQ(irqn);
}
/**
* @brief config nvic priority group
* @param priority_group
* this parameter can be one of the following values:
* - NVIC_PRIORITY_GROUP_0
* - NVIC_PRIORITY_GROUP_1
* - NVIC_PRIORITY_GROUP_2
* - NVIC_PRIORITY_GROUP_3
* - NVIC_PRIORITY_GROUP_4
* @retval none
*/
void nvic_priority_group_config(nvic_priority_group_type priority_group)
{
/* set the prigroup[10:8] bits according to nvic_prioritygroup value */
NVIC_SetPriorityGrouping(priority_group);
}
/**
* @brief set the vector table location and offset.
* @param base
* this parameter can be one of the following values:
* - NVIC_VECTTAB_RAM
* - NVIC_VECTTAB_FLASH
* @param offset (vector table base offset field. this value must be a multiple of 0x200)
* @retval none
*/
void nvic_vector_table_set(uint32_t base, uint32_t offset)
{
SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief config nvic lowpower mode
* @param lp_mode
* this parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
* @param new_state (new state of lp condition. ENABLE or DISABLE)
* @retval none
*/
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
SCB->SCR |= lp_mode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
}
}
/**
* @brief config systick clock source
* @param source
* this parameter can be one of the following values:
* - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
* - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
* @retval none
*/
void systick_clock_source_config(systick_clock_source_type source)
{
if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
{
SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
else
{
SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_pwc.c
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup PWC
* @brief PWC driver modules
* @{
*/
#ifdef PWC_MODULE_ENABLED
/** @defgroup PWC_private_functions
* @{
*/
/**
* @brief deinitialize the pwc peripheral registers to their default reset values.
* @param none
* @retval none
*/
void pwc_reset(void)
{
crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable access to the battery powered domain.
* @param new_state: new state of battery powered domain access.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_battery_powered_domain_access(confirm_state new_state)
{
PWC->ctrl_bit.bpwen = new_state;
}
/**
* @brief select the voltage threshold detected by the power voltage detector.
* @param pvm_voltage: select pwc pvm voltage
* this parameter can be one of the following values:
* - PWC_PVM_VOLTAGE_2V3
* - PWC_PVM_VOLTAGE_2V4
* - PWC_PVM_VOLTAGE_2V5
* - PWC_PVM_VOLTAGE_2V6
* - PWC_PVM_VOLTAGE_2V7
* - PWC_PVM_VOLTAGE_2V8
* - PWC_PVM_VOLTAGE_2V9
* @retval none
*/
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
{
PWC->ctrl_bit.pvmsel = pvm_voltage;
}
/**
* @brief enable or disable pwc power voltage monitor (pvm)
* @param new_state: new state of pvm.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_power_voltage_monitor_enable(confirm_state new_state)
{
PWC->ctrl_bit.pvmen = new_state;
}
/**
* @brief enable or disable pwc standby wakeup pin
* @param pin_num: choose the wakeup pin.
* this parameter can be be any combination of the following values:
* - PWC_WAKEUP_PIN_1
* - PWC_WAKEUP_PIN_2
* - PWC_WAKEUP_PIN_6
* - PWC_WAKEUP_PIN_7
* @param new_state: new state of the standby wakeup pin.
* this parameter can be one of the following values:
* - TRUE <wakeup pin is used for wake up cpu from standby mode>
* - FALSE <wakeup pin is used for general purpose I/O>
* @retval none
*/
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
{
if(new_state == TRUE)
{
PWC->ctrlsts |= pin_num;
}
else
{
PWC->ctrlsts &= ~pin_num;
}
}
/**
* @brief clear flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be any combination of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
* @retval none
*/
void pwc_flag_clear(uint32_t pwc_flag)
{
if(pwc_flag & PWC_STANDBY_FLAG)
PWC->ctrl_bit.clsef = TRUE;
if(pwc_flag & PWC_WAKEUP_FLAG)
PWC->ctrl_bit.clswef = TRUE;
}
/**
* @brief get flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be one of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - PWC_PVM_OUTPUT_FLAG
* @retval state of select flag(SET or RESET).
*/
flag_status pwc_flag_get(uint32_t pwc_flag)
{
flag_status status = RESET;
if ((PWC->ctrlsts & pwc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief enter pwc sleep mode
* @param sleep_mode_enter: choose the instruction to enter sleep mode.
* this parameter can be one of the following values:
* - PWC_SLEEP_ENTER_WFI
* - PWC_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
{
SCB->SCR &= (uint32_t)~0x4;
if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
{
__WFI();
}
}
/**
* @brief enter pwc deep-sleep mode
* @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
* this parameter can be one of the following values:
* - PWC_DEEP_SLEEP_ENTER_WFI
* - PWC_DEEP_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
{
SCB->SCR |= 0x04;
if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
{
__WFI();
}
SCB->SCR &= (uint32_t)~0x4;
}
/**
* @brief regulate low power consumption in the deep sleep mode
* @param pwc_regulator: set the regulator state.
* this parameter can be one of the following values:
* - PWC_REGULATOR_ON
* - PWC_REGULATOR_LOW_POWER
* @retval none
*/
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
{
switch(pwc_regulator)
{
case PWC_REGULATOR_ON:
PWC->ctrl_bit.vrsel = FALSE;
break;
case PWC_REGULATOR_LOW_POWER:
PWC->ctrl_bit.vrsel = TRUE;
break;
default:
break;
}
}
/**
* @brief enter pwc standby mode
* @param none
* @retval none
*/
void pwc_standby_mode_enter(void)
{
PWC->ctrl_bit.clswef = TRUE;
PWC->ctrl_bit.lpsel = TRUE;
SCB->SCR |= 0x04;
#if defined (__CC_ARM)
__force_stores();
#endif
while(1)
{
__WFI();
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_scfg.c
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup SCFG
* @brief SCFG driver modules
* @{
*/
#ifdef SCFG_MODULE_ENABLED
/** @defgroup SCFG_private_functions
* @{
*/
/**
* @brief scfg reset
* @param none
* @retval none
*/
void scfg_reset(void)
{
crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
}
/**
* @brief scfg infrared config
* @param source
* this parameter can be one of the following values:
* - SCFG_IR_SOURCE_TMR16
* @param polarity
* this parameter can be one of the following values:
* - SCFG_IR_POLARITY_NO_AFFECTE
* - SCFG_IR_POLARITY_REVERSE
* @retval none
*/
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
{
SCFG->cfg1_bit.ir_src_sel = source;
SCFG->cfg1_bit.ir_pol = polarity;
}
/**
* @brief scfg memory address mapping get
* @param none
* @retval return parameter can be one of the following values:
* - SCFG_MEM_MAP_MAIN_MEMORY
* - SCFG_MEM_MAP_BOOT_MEMORY
* - SCFG_MEM_MAP_INTERNAL_SRAM
*/
uint8_t scfg_mem_map_get(void)
{
return (uint8_t)SCFG->cfg1_bit.mem_map_sel ;
}
/**
* @brief scfg pa11/12 pin remap
* @param pin_remap
* this parameter can be one of the following values:
* - SCFG_PA11PA12_NO_REMAP
* - SCFG_PA11PA12_TO_PA9PA10
* @retval none
*/
void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap)
{
SCFG->cfg1_bit.pa11_12_rmp = pin_remap;
}
/**
* @brief scfg adc dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_ADC_TO_DMA_CHANNEL_1
* - SCFG_ADC_TO_DMA_CHANNEL_2
* @retval none
*/
void scfg_adc_dma_channel_remap(scfg_adc_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.adc_dma_rmp = dma_channel;
}
/**
* @brief scfg usart1 tx dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_USART1_TX_TO_DMA_CHANNEL_2
* - SCFG_USART1_TX_TO_DMA_CHANNEL_4
* @retval none
*/
void scfg_usart1_tx_dma_channel_remap(scfg_usart1_tx_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.usart1_tx_dma_rmp = dma_channel;
}
/**
* @brief scfg usart1 rx dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_USART1_RX_TO_DMA_CHANNEL_3
* - SCFG_USART1_RX_TO_DMA_CHANNEL_5
* @retval none
*/
void scfg_usart1_rx_dma_channel_remap(scfg_usart1_rx_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.usart1_rx_dma_rmp = dma_channel;
}
/**
* @brief scfg tmr16 dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_TMR16_TO_DMA_CHANNEL_3
* - SCFG_TMR16_TO_DMA_CHANNEL_4
* @retval none
*/
void scfg_tmr16_dma_channel_remap(scfg_tmr16_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.tmr16_dma_rmp = dma_channel;
}
/**
* @brief scfg tmr17 dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_TMR17_TO_DMA_CHANNEL_1
* - SCFG_TMR17_TO_DMA_CHANNEL_2
* @retval none
*/
void scfg_tmr17_dma_channel_remap(scfg_tmr17_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.tmr17_dma_rmp = dma_channel;
}
/**
* @brief select the gpio pin used as exint line.
* @param port_source:
* select the gpio port to be used as source for exint lines.
* this parameter can be one of the following values:
* - SCFG_PORT_SOURCE_GPIOA
* - SCFG_PORT_SOURCE_GPIOB
* - SCFG_PORT_SOURCE_GPIOC
* - SCFG_PORT_SOURCE_GPIOF
* @param pin_source:
* specifies the exint line to be configured.
* this parameter can be one of the following values:
* - SCFG_PINS_SOURCE0
* - SCFG_PINS_SOURCE1
* - SCFG_PINS_SOURCE2
* - SCFG_PINS_SOURCE3
* - SCFG_PINS_SOURCE4
* - SCFG_PINS_SOURCE5
* - SCFG_PINS_SOURCE6
* - SCFG_PINS_SOURCE7
* - SCFG_PINS_SOURCE8
* - SCFG_PINS_SOURCE9
* - SCFG_PINS_SOURCE10
* - SCFG_PINS_SOURCE11
* - SCFG_PINS_SOURCE12
* - SCFG_PINS_SOURCE13
* - SCFG_PINS_SOURCE14
* - SCFG_PINS_SOURCE15
* @retval none
*/
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
switch (pin_source >> 0x02)
{
case 0:
SCFG->exintc1 &= ~tmp;
SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 1:
SCFG->exintc2 &= ~tmp;
SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 2:
SCFG->exintc3 &= ~tmp;
SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 3:
SCFG->exintc4 &= ~tmp;
SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
default:
break;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

675
vd960Loop/libraries/drivers/src/at32f421_spi.c Normal file
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@@ -0,0 +1,675 @@
/**
**************************************************************************
* @file at32f421_spi.c
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
#ifdef SPI_MODULE_ENABLED
/** @defgroup SPI_private_functions
* @{
*/
/**
* @brief spi reset by crm reset register
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval none
*/
void spi_i2s_reset(spi_type *spi_x)
{
if(spi_x == SPI1)
{
crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
}
#if defined (AT32F421Cx) || defined (AT32F421Kx) || defined (AT32F421Gx)
else if(spi_x == SPI2)
{
crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
}
#endif
}
/**
* @brief spi init config with its default value.
* @param spi_init_struct : pointer to a spi_init_type structure which will
* be initialized.
* @retval none
*/
void spi_default_para_init(spi_init_type* spi_init_struct)
{
spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
}
/**
* @brief spi init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
* @retval none
*/
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
{
spi_x->i2sctrl_bit.i2smsel = FALSE;
if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = TRUE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = TRUE;
spi_x->ctrl1_bit.ora = FALSE;
}
spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
{
spi_x->ctrl1_bit.swcsil = TRUE;
}
else
{
spi_x->ctrl1_bit.swcsil = FALSE;
}
spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
if(spi_init_struct->mclk_freq_division > SPI_MCLK_DIV_256)
{
spi_x->ctrl2_bit.mdiv_h = 1;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
}
else
{
spi_x->ctrl2_bit.mdiv_h = 0;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
}
spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
}
/**
* @brief spi next transmit crc for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval none
*/
void spi_crc_next_transmit(spi_type* spi_x)
{
spi_x->ctrl1_bit.ntc = TRUE;
}
/**
* @brief set the crc polynomial value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param crc_poly: crc polynomial value.
* @retval none
*/
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
{
spi_x->cpoly_bit.cpoly = crc_poly;
}
/**
* @brief return the crc polynomial register value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval the select crc polynomial register value
*/
uint16_t spi_crc_polynomial_get(spi_type* spi_x)
{
return spi_x->cpoly_bit.cpoly;
}
/**
* @brief enable or disable the hardware crc calculation for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of crc calculation.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.ccen = new_state;
}
/**
* @brief return the transmit or the receive crc value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param crc_direction: select transmit or receive crc value to be read
* - SPI_CRC_RX
* - SPI_CRC_TX
* @retval the select crc register value
*/
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
{
if(crc_direction == SPI_CRC_RX)
return spi_x->rcrc_bit.rcrc;
else
return spi_x->tcrc_bit.tcrc;
}
/**
* @brief enable or disable the hardware cs output for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of spi master cs output.
* this parameter can be: TRUE or FALSE.
* note:the bit only use in spi master mode
* @retval none
*/
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.hwcsoe = new_state;
}
/**
* @brief set the software cs internal level for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param level: set the state of spi cs level.
* this parameter can be one of the following values:
* - SPI_SWCS_INTERNAL_LEVEL_LOW
* - SPI_SWCS_INTERNAL_LEVEL_HIGHT
* note:the bit only use when swcsen bit is set.
* note:when use this bit,io operation on the cs pin are invalid.
* @retval none
*/
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
{
spi_x->ctrl1_bit.swcsil = level;
}
/**
* @brief set the data frame bit num for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param bit_num: set the data frame size
* - SPI_FRAME_8BIT
* - SPI_FRAME_16BIT
* @retval none
*/
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
{
spi_x->ctrl1_bit.fbn = bit_num;
}
/**
* @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param direction: data transfer direction
* this parameter can be one of the following values:
* - SPI_HALF_DUPLEX_DIRECTION_RX
* - SPI_HALF_DUPLEX_DIRECTION_TX
* @retval none
*/
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
{
spi_x->ctrl1_bit.slbtd = direction;
}
/**
* @brief enable or disable spi.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of spi.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.spien = new_state;
}
/**
* @brief i2s init config with its default value.
* @param i2s_init_struct : pointer to a i2s_init_type structure which will
* be initialized.
* @retval none
*/
void i2s_default_para_init(i2s_init_type* i2s_init_struct)
{
i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
i2s_init_struct->mclk_output_enable = FALSE;
}
/**
* @brief i2s init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
* @retval none
*/
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
{
crm_clocks_freq_type clocks_freq;
uint32_t i2s_sclk_index = 0;
uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
/* i2s audio frequency config */
if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
else
{
crm_clocks_freq_get(&clocks_freq);
i2s_sclk_index = clocks_freq.sclk_freq;
if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
else
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
}
frequency_index = frequency_index / 10;
i2sodd_index = frequency_index & (uint16_t)0x0001;
i2sdiv_index = (frequency_index - i2sodd_index) / 2;
if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
spi_x->i2sclk_bit.i2sodd = i2sodd_index;
if(i2sdiv_index > 0x00FF)
{
spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
}
else
{
spi_x->i2sclk_bit.i2sdiv_h = 0;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
}
/* i2s audio_protocol set*/
if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
{
spi_x->i2sctrl_bit.pcmfssel = 1;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 2;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 1;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 0;
}
/* i2s data_channel_format set*/
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
{
spi_x->i2sctrl_bit.i2scbn = 0;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 1;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 2;
}
spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
spi_x->i2sctrl_bit.i2smsel = TRUE;
}
/**
* @brief enable or disable i2s.
* @param spi_x: select the i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of i2s.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void i2s_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->i2sctrl_bit.i2sen = new_state;
}
/**
* @brief enable or disable the specified spi/i2s interrupts.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - SPI_I2S_ERROR_INT
* - SPI_I2S_RDBF_INT
* - SPI_I2S_TDBE_INT
* @param new_state: new state of the specified spi/i2s interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
{
if(new_state != FALSE)
{
spi_x->ctrl2 |= spi_i2s_int;
}
else
{
spi_x->ctrl2 &= ~spi_i2s_int;
}
}
/**
* @brief enable or disable the spi/i2s dma transmitter mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaten = new_state;
}
/**
* @brief enable or disable the spi/i2s dma receiver mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaren = new_state;
}
/**
* @brief spi/i2s data transmit
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param tx_data: the data to be transmit.
* this parameter can be:
* - (0x0000~0xFFFF)
* @retval none
*/
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
{
spi_x->dt = tx_data;
}
/**
* @brief spi/i2s data receive
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval the received data value
*/
uint16_t spi_i2s_data_receive(spi_type* spi_x)
{
return (uint16_t)spi_x->dt;
}
/**
* @brief get flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_ACS_FLAG (this flag only use in i2s mode)
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* - SPI_I2S_BF_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
if ((spi_x->sts & spi_i2s_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
switch(spi_i2s_flag)
{
case SPI_I2S_RDBF_FLAG:
if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
{
status = SET;
}
break;
case SPI_I2S_TDBE_FLAG:
if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
{
status = SET;
}
break;
case I2S_TUERR_FLAG:
if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_CCERR_FLAG:
if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_MMERR_FLAG:
if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_I2S_ROERR_FLAG:
if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
default:
break;
};
return status;
}
/**
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_CCERR_FLAG
* - SPI_I2S_RDBF_FLAG
* - I2S_TUERR_FLAG
* - SPI_MMERR_FLAG
* - SPI_I2S_ROERR_FLAG
* @note
* SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
* I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
* SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
* @retval none
*/
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
UNUSED(spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_MMERR_FLAG)
{
UNUSED(spi_x->sts);
spi_x->ctrl1 = spi_x->ctrl1;
}
else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
{
UNUSED(spi_x->dt);
UNUSED(spi_x->sts);
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_usart.c
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup USART
* @brief USART driver modules
* @{
*/
#ifdef USART_MODULE_ENABLED
/** @defgroup USART_private_functions
* @{
*/
/**
* @brief deinitialize the usart peripheral registers to their default reset values.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval none
*/
void usart_reset(usart_type* usart_x)
{
if(usart_x == USART1)
{
crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
}
else if(usart_x == USART2)
{
crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the usart peripheral according to the specified parameters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param baud_rate: configure the usart communication baud rate.
* @param data_bit: data bits transmitted or received in a frame
* this parameter can be one of the following values:
* - USART_DATA_8BITS
* - USART_DATA_9BITS.
* note：
* - when parity check is disabled, the data bit width is the actual data bit number.
* - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
* @param stop_bit: stop bits transmitted
* this parameter can be one of the following values:
* - USART_STOP_1_BIT
* - USART_STOP_0_5_BIT.
* - USART_STOP_2_BIT
* - USART_STOP_1_5_BIT.
* @retval none
*/
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
{
crm_clocks_freq_type clocks_freq;
uint32_t apb_clock, temp_val;
crm_clocks_freq_get(&clocks_freq);
if(usart_x == USART1)
{
apb_clock = clocks_freq.apb2_freq;
}
else
{
apb_clock = clocks_freq.apb1_freq;
}
temp_val = (apb_clock * 10 / baud_rate);
if((temp_val % 10) < 5)
{
temp_val = (temp_val / 10);
}
else
{
temp_val = (temp_val / 10) + 1;
}
usart_x->baudr_bit.div = temp_val;
usart_x->ctrl1_bit.dbn = data_bit;
usart_x->ctrl2_bit.stopbn = stop_bit;
}
/**
* @brief usart parity selection config.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param parity: select the none, odd or even parity.
* this parameter can be one of the following values:
* - USART_PARITY_NONE
* - USART_PARITY_EVEN.
* - USART_PARITY_ODD
* @retval none
*/
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
{
if(parity == USART_PARITY_NONE)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = FALSE;
}
else if(parity == USART_PARITY_EVEN)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = TRUE;
}
else if(parity == USART_PARITY_ODD)
{
usart_x->ctrl1_bit.psel = TRUE;
usart_x->ctrl1_bit.pen = TRUE;
}
}
/**
* @brief enable or disable the specified usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.uen = new_state;
}
/**
* @brief usart transmitter enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ten = new_state;
}
/**
* @brief usart receiver enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ren = new_state;
}
/**
* @brief usart clock config.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param clk_pol: polarity of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_POLARITY_LOW
* - USART_CLOCK_POLARITY_HIGH
* @param clk_pha: phase of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_PHASE_1EDGE
* - USART_CLOCK_PHASE_2EDGE
* @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_LAST_BIT_NONE
* - USART_CLOCK_LAST_BIT_OUTPUT
* @retval none
*/
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
{
usart_x->ctrl2_bit.clkpol = clk_pol;
usart_x->ctrl2_bit.clkpha = clk_pha;
usart_x->ctrl2_bit.lbcp = clk_lb;
}
/**
* @brief usart enable the ck pin.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE
* @retval none
*/
void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.clken = new_state;
}
/**
* @brief enable or disable the specified usart interrupts.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - USART_IDLE_INT: idle interrupt
* - USART_RDBF_INT: rdbf interrupt
* - USART_TDC_INT: tdc interrupt
* - USART_TDBE_INT: tdbe interrupt
* - USART_PERR_INT: perr interrupt
* - USART_BF_INT: break frame interrupt
* - USART_ERR_INT: err interrupt
* - USART_CTSCF_INT: ctscf interrupt
* @param new_state: new state of the specified usart interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
{
if(new_state == TRUE)
PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
else
PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
}
/**
* @brief enable or disable the usart's dma transmitter interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaten = new_state;
}
/**
* @brief enable or disable the usart's dma receiver interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaren = new_state;
}
/**
* @brief set the wakeup id of the usart.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param usart_id: the matching id(0x0~0xF).
* @retval none
*/
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
{
usart_x->ctrl2_bit.id = usart_id;
}
/**
* @brief select the usart wakeup method in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param wakeup_mode: determines the way to wake up usart method.
* this parameter can be one of the following values:
* - USART_WAKEUP_BY_IDLE_FRAME
* - USART_WAKEUP_BY_MATCHING_ID
* @retval none
*/
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
{
usart_x->ctrl1_bit.wum = wakeup_mode;
}
/**
* @brief config the usart in mute mode in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart mute mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.rm = new_state;
}
/**
* @brief set the usart break frame bit num.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param break_bit: specifies the break bit num.
* this parameter can be one of the following values:
* - USART_BREAK_10BITS
* - USART_BREAK_11BITS
* @retval none
*/
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
{
usart_x->ctrl2_bit.bfbn = break_bit;
}
/**
* @brief enable or disable the usart lin mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart lin mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.linen = new_state;
}
/**
* @brief transmit single data through the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param data: the data to transmit.
* @retval none
*/
void usart_data_transmit(usart_type* usart_x, uint16_t data)
{
usart_x->dt = (data & 0x01FF);
}
/**
* @brief return the most recent received data by the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval the received data.
*/
uint16_t usart_data_receive(usart_type* usart_x)
{
return (uint16_t)(usart_x->dt);
}
/**
* @brief transmit break characters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval none
*/
void usart_break_send(usart_type* usart_x)
{
usart_x->ctrl1_bit.sbf = TRUE;
}
/**
* @brief config the specified usart smartcard guard time.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param guard_time_val: specifies the guard time (0x00~0xFF).
* @retval none
*/
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
{
usart_x->gdiv_bit.scgt = guard_time_val;
}
/**
* @brief config the irda/smartcard division.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param div_val: specifies the division.
* @retval none
*/
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
{
usart_x->gdiv_bit.isdiv = div_val;
}
/**
* @brief enable or disable the usart smart card mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the smart card mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scmen = new_state;
}
/**
* @brief enable or disable nack transmission in smartcard mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the nack transmission.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scnacken = new_state;
}
/**
* @brief enable or disable the usart single line bidirectional half-duplex communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the single line half-duplex select.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.slben = new_state;
}
/**
* @brief enable or disable the usart's irda interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdaen = new_state;
}
/**
* @brief configure the usart's irda low power.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdalp = new_state;
}
/**
* @brief configure the usart's hardware flow control.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flow_state: specifies the hardware flow control.
* this parameter can be one of the following values:
* - USART_HARDWARE_FLOW_NONE
* - USART_HARDWARE_FLOW_RTS,
* - USART_HARDWARE_FLOW_CTS,
* - USART_HARDWARE_FLOW_RTS_CTS
* @retval none
*/
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
{
if(flow_state == USART_HARDWARE_FLOW_NONE)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_CTS)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
}
/**
* @brief swap the usart's transmit receive pin.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.trpswap = new_state;
}
/**
* @brief check whether the specified usart flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
{
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief check whether the specified usart interrupt flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5)
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
{
flag_status int_status = RESET;
switch(flag)
{
case USART_CTSCF_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
break;
case USART_BFF_FLAG:
int_status = (flag_status)usart_x->ctrl2_bit.bfien;
break;
case USART_TDBE_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
break;
case USART_TDC_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
break;
case USART_RDBF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
break;
case USART_ROERR_FLAG:
int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
break;
case USART_IDLEF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
break;
case USART_NERR_FLAG:
case USART_FERR_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.errien;
break;
case USART_PERR_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
break;
default:
int_status = RESET;
break;
}
if(int_status != SET)
{
return RESET;
}
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear the usart's pending flags.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to clear.
* this parameter can be any combination of the following values:
* - USART_CTSCF_FLAG: (not available for UART4,UART5,USART6,UART7 and UART8).
* - USART_BFF_FLAG:
* - USART_TDC_FLAG:
* - USART_RDBF_FLAG:
* - USART_PERR_FLAG:
* - USART_FERR_FLAG:
* - USART_NERR_FLAG:
* - USART_ROERR_FLAG:
* - USART_IDLEF_FLAG:
* @note
* - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
* sequence: a read operation to usart sts register (usart_flag_get())
* followed by a read operation to usart dt register (usart_data_receive()).
* - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
* - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
* followed by a write operation to usart dt register (usart_data_transmit()).
* - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
* @retval none
*/
void usart_flag_clear(usart_type* usart_x, uint32_t flag)
{
if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
{
UNUSED(usart_x->sts);
UNUSED(usart_x->dt);
}
else
{
usart_x->sts = ~flag;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_wdt.c
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup WDT
* @brief WDT driver modules
* @{
*/
#ifdef WDT_MODULE_ENABLED
/** @defgroup WDT_private_functions
* @{
*/
/**
* @brief wdt enable ,the reload value will be sent to the counter
* @param none
* @retval none
*/
void wdt_enable(void)
{
WDT->cmd = WDT_CMD_ENABLE;
}
/**
* @brief reload wdt counter
* @param none
* @retval none
*/
void wdt_counter_reload(void)
{
WDT->cmd = WDT_CMD_RELOAD;
}
/**
* @brief set wdt counter reload value
* @param reload_value (0x0000~0x0FFF)
* @retval none
*/
void wdt_reload_value_set(uint16_t reload_value)
{
WDT->rld = reload_value;
}
/**
* @brief set wdt division divider
* @param division
* this parameter can be one of the following values:
* - WDT_CLK_DIV_4
* - WDT_CLK_DIV_8
* - WDT_CLK_DIV_16
* - WDT_CLK_DIV_32
* - WDT_CLK_DIV_64
* - WDT_CLK_DIV_128
* - WDT_CLK_DIV_256
* @retval none
*/
void wdt_divider_set(wdt_division_type division)
{
WDT->div_bit.div = division;
}
/**
* @brief enable or disable wdt cmd register write
* @param new_state (TRUE or FALSE)
* @retval none
*/
void wdt_register_write_enable( confirm_state new_state)
{
if(new_state == FALSE)
{
WDT->cmd = WDT_CMD_LOCK;
}
else
{
WDT->cmd = WDT_CMD_UNLOCK;
}
}
/**
* @brief get wdt flag
* @param wdt_flag
* this parameter can be one of the following values:
* - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
* - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
* @retval state of wdt flag
*/
flag_status wdt_flag_get(uint16_t wdt_flag)
{
flag_status status = RESET;
if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/

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/**
**************************************************************************
* @file at32f421_wwdt.c
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup WWDT
* @brief WWDT driver modules
* @{
*/
#ifdef WWDT_MODULE_ENABLED
/** @defgroup WWDT_private_functions
* @{
*/
/**
* @brief wwdt reset by crm reset register
* @retval none
*/
void wwdt_reset(void)
{
crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
}
/**
* @brief wwdt division set
* @param division
* this parameter can be one of the following values:
* - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
* - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
* - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
* - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
* @retval none
*/
void wwdt_divider_set(wwdt_division_type division)
{
WWDT->cfg_bit.div = division;
}
/**
* @brief wwdt reload counter interrupt flag clear
* @param none
* @retval none
*/
void wwdt_flag_clear(void)
{
WWDT->sts = 0;
}
/**
* @brief wwdt enable and the counter value load
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_enable(uint8_t wwdt_cnt)
{
WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
}
/**
* @brief wwdt reload counter interrupt enable
* @param none
* @retval none
*/
void wwdt_interrupt_enable(void)
{
WWDT->cfg_bit.rldien = TRUE;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_flag_get(void)
{
return (flag_status)WWDT->sts_bit.rldf;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_interrupt_flag_get(void)
{
return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
}
/**
* @brief wwdt counter value set
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_counter_set(uint8_t wwdt_cnt)
{
WWDT->ctrl_bit.cnt = wwdt_cnt;
}
/**
* @brief wwdt window counter value set
* @param window_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_window_counter_set(uint8_t window_cnt)
{
WWDT->cfg_bit.win = window_cnt;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/