95808f9f25
- 用 DLD154V4B vd1_task/per_channel 替换 vds_task 复杂算法
- 移除 FUNCTION_B/二次判断/快速变化/多重确认等增强特性
- 保留平坦性离开算法 (CN200910309382)，每通道独立状态
- 灵敏度表改为 DLD154V4B 4级: {216,108,36,10} / {108,72,18,9}
- 清理废弃类型: FltHistoryManager, Loop_ACS_Info, StageRangeConfig 等
- 首次添加 vd960DBN 完整源码
306 lines
9.1 KiB
C
306 lines
9.1 KiB
C
/**
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**************************************************************************
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* @file at32f421_scfg.h
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* @brief at32f421 system config header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F421_SCFG_H
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#define __AT32F421_SCFG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f421.h"
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/** @addtogroup AT32F421_periph_driver
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* @{
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*/
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/** @addtogroup SCFG
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* @{
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*/
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#define SCFG_REG(value) PERIPH_REG(SCFG_CMP_BASE, value)
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#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
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/** @defgroup SCFG_exported_types
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* @{
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*/
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/**
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* @brief scfg infrared modulation signal source selecting type
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*/
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typedef enum
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{
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SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */
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} scfg_ir_source_type;
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/**
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* @brief scfg pa11 pa12 pin remap type
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*/
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typedef enum
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{
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SCFG_PA11PA12_NO_REMAP = 0x00, /* pa11 pa12 pin no remap */
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SCFG_PA11PA12_TO_PA9PA10 = 0x01, /* pa11 pa12 pin remap pa9 pa10*/
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} scfg_pa11pa12_remap_type;
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/**
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* @brief scfg adc dma channel remap type
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*/
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typedef enum
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{
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SCFG_ADC_TO_DMA_CHANNEL_1 = 0x00, /* adc config to dma channel 1 */
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SCFG_ADC_TO_DMA_CHANNEL_2 = 0x01, /* adc config to dma channel 2*/
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} scfg_adc_dma_remap_type;
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/**
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* @brief scfg usart1 tx dma channel remap type
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*/
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typedef enum
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{
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SCFG_USART1_TX_TO_DMA_CHANNEL_2 = 0x00, /* usart1 tx config to dma channel 2 */
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SCFG_USART1_TX_TO_DMA_CHANNEL_4 = 0x01, /* usart1 tx config to dma channel 4 */
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} scfg_usart1_tx_dma_remap_type;
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/**
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* @brief scfg usart1 rx dma channel remap type
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*/
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typedef enum
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{
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SCFG_USART1_RX_TO_DMA_CHANNEL_3 = 0x00, /* usart1 rx config to dma channel 3 */
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SCFG_USART1_RX_TO_DMA_CHANNEL_5 = 0x01, /* usart1 rx config to dma channel 5 */
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} scfg_usart1_rx_dma_remap_type;
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/**
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* @brief scfg tmr16 dma channel remap type
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*/
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typedef enum
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{
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SCFG_TMR16_TO_DMA_CHANNEL_3 = 0x00, /* tmr16 config to dma channel 3 */
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SCFG_TMR16_TO_DMA_CHANNEL_4 = 0x01, /* tmr16 config to dma channel 4 */
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} scfg_tmr16_dma_remap_type;
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/**
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* @brief scfg tmr17 dma channel remap type
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*/
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typedef enum
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{
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SCFG_TMR17_TO_DMA_CHANNEL_1 = 0x00, /* tmr17 config to dma channel 1 */
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SCFG_TMR17_TO_DMA_CHANNEL_2 = 0x01, /* tmr17 config to dma channel 2 */
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} scfg_tmr17_dma_remap_type;
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/**
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* @brief scfg infrared output polarity selecting type
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*/
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typedef enum
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{
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SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
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SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
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} scfg_ir_polarity_type;
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/**
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* @brief scfg memory address mapping selecting type
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*/
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typedef enum
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{
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SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
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SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
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SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
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} scfg_mem_map_type;
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/**
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* @brief scfg pin source type
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*/
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typedef enum
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{
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SCFG_PINS_SOURCE0 = 0x00,
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SCFG_PINS_SOURCE1 = 0x01,
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SCFG_PINS_SOURCE2 = 0x02,
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SCFG_PINS_SOURCE3 = 0x03,
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SCFG_PINS_SOURCE4 = 0x04,
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SCFG_PINS_SOURCE5 = 0x05,
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SCFG_PINS_SOURCE6 = 0x06,
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SCFG_PINS_SOURCE7 = 0x07,
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SCFG_PINS_SOURCE8 = 0x08,
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SCFG_PINS_SOURCE9 = 0x09,
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SCFG_PINS_SOURCE10 = 0x0A,
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SCFG_PINS_SOURCE11 = 0x0B,
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SCFG_PINS_SOURCE12 = 0x0C,
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SCFG_PINS_SOURCE13 = 0x0D,
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SCFG_PINS_SOURCE14 = 0x0E,
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SCFG_PINS_SOURCE15 = 0x0F
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} scfg_pins_source_type;
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/**
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* @brief gpio port source type
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*/
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typedef enum
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{
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SCFG_PORT_SOURCE_GPIOA = 0x00,
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SCFG_PORT_SOURCE_GPIOB = 0x01,
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SCFG_PORT_SOURCE_GPIOC = 0x02,
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SCFG_PORT_SOURCE_GPIOF = 0x05,
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} scfg_port_source_type;
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/**
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* @brief type define system config register all
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*/
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typedef struct
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{
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/**
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* @brief scfg cfg1 register, offset:0x00
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*/
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union
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{
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__IO uint32_t cfg1;
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struct
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{
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__IO uint32_t mem_map_sel : 2; /* [1:0] */
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__IO uint32_t reserved1 : 2; /* [3:2] */
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__IO uint32_t pa11_12_rmp : 1; /* [4] */
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__IO uint32_t ir_pol : 1; /* [5] */
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__IO uint32_t ir_src_sel : 2; /* [7:6] */
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__IO uint32_t adc_dma_rmp : 1; /* [8] */
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__IO uint32_t usart1_tx_dma_rmp : 1; /* [9] */
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__IO uint32_t usart1_rx_dma_rmp : 1; /* [10] */
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__IO uint32_t tmr16_dma_rmp : 1; /* [11] */
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__IO uint32_t tmr17_dma_rmp : 1; /* [12] */
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__IO uint32_t reserved2 : 19;/* [31:13] */
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} cfg1_bit;
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};
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/**
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* @brief scfg reserved1 register, offset:0x04
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*/
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__IO uint32_t reserved1;
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/**
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* @brief scfg exintc1 register, offset:0x08
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*/
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union
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{
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__IO uint32_t exintc1;
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struct
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{
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__IO uint32_t exint0 : 4; /* [3:0] */
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__IO uint32_t exint1 : 4; /* [7:4] */
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__IO uint32_t exint2 : 4; /* [11:8] */
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__IO uint32_t exint3 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc1_bit;
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};
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/**
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* @brief scfg exintc2 register, offset:0x0C
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*/
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union
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{
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__IO uint32_t exintc2;
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struct
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{
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__IO uint32_t exint4 : 4; /* [3:0] */
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__IO uint32_t exint5 : 4; /* [7:4] */
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__IO uint32_t exint6 : 4; /* [11:8] */
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__IO uint32_t exint7 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc2_bit;
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};
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/**
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* @brief scfg exintc3 register, offset:0x10
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*/
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union
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{
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__IO uint32_t exintc3;
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struct
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{
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__IO uint32_t exint8 : 4; /* [3:0] */
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__IO uint32_t exint9 : 4; /* [7:4] */
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__IO uint32_t exint10 : 4; /* [11:8] */
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__IO uint32_t exint11 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc3_bit;
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};
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/**
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* @brief scfg exintc4 register, offset:0x14
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*/
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union
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{
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__IO uint32_t exintc4;
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struct
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{
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__IO uint32_t exint12 : 4; /* [3:0] */
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__IO uint32_t exint13 : 4; /* [7:4] */
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__IO uint32_t exint14 : 4; /* [11:8] */
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__IO uint32_t exint15 : 4; /* [15:12] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} exintc4_bit;
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};
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} scfg_type;
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/**
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* @}
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*/
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#define SCFG ((scfg_type *) SCFG_CMP_BASE)
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/** @defgroup SCFG_exported_functions
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* @{
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*/
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void scfg_reset(void);
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void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
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uint8_t scfg_mem_map_get(void);
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void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap);
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void scfg_adc_dma_channel_remap(scfg_adc_dma_remap_type dma_channel);
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void scfg_usart1_tx_dma_channel_remap(scfg_usart1_tx_dma_remap_type dma_channel);
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void scfg_usart1_rx_dma_channel_remap(scfg_usart1_rx_dma_remap_type dma_channel);
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void scfg_tmr16_dma_channel_remap(scfg_tmr16_dma_remap_type dma_channel);
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void scfg_tmr17_dma_channel_remap(scfg_tmr17_dma_remap_type dma_channel);
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void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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