wangfq/vd_960
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 4 Wiki Activity

feat(vd960Loop): 看门狗升级双保险喂狗模式 + 超时对齐 V4B（1.64s）

Browse Source 
对照 DLD154V4B V2.10（同款 AT32F421）:
- 原直喂模式缺 ISR 活性检测: TMR15 ISR 死但主循环活 -> 看门狗永不复位(假活)
- 升级: TMR15 ISR 5ms 递增 g_wdg_counter + 主循环 poll_wdg() 500ms 才 reload
- 超时 3s(div64/rld1875) -> 1.64s(div16枚举/rld4095)
- wdt_feed 定义移至 TaskLoop.c 改名 poll_wdg, 与 V4B 同构
- 修正 main.c 注释矛盾(4687 vs 1875); 沿用 WDT_CLK_DIV_16 枚举写法避免
  V4B 同源传值 bug
- 隔离测试 3 项断言全过(分频16/超时1638ms>500ms/10s喂20次/ISR死不喂)
This commit is contained in:
wangfq
2026-08-28 09:15:25 +08:00
parent 40e6648445
commit fd1e1ee167
60 changed files with 21386 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
DLD960LoopBootloader/.gitignore
+51
View File
@@ -0,0 +1,51 @@
/.vs
MDK-ARM/
RTE/
settings/
*.cproject
*.settings/
*.uvguix*
*.uvprojx
*.uvoptx
*.crf
*.TMP
*.o
*.obj
*.out
*.dep
*.i
*.d
*.old
obj/
*.lst
*.hex
*.map
*.__i
*.htm
*.html
*.axf
*.bak
iar_v6.10/
iar_v7.4/
iar_v8.2/
templates/
*.pdf
*.chm
*.txt
*.exe
doc/
iar/
*.xml
examples/
3rd_party/
dsp/
cmsis/
middlewares/
objects/
listings/
DLD960LoopBootloader/libraries/drivers/inc/at32f421_adc.h
+584
View File
@@ -0,0 +1,584 @@
/**
**************************************************************************
* @file at32f421_adc.h
* @brief at32f421 adc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_ADC_H
#define __AT32F421_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_interrupts_definition
* @brief adc interrupt
* @{
*/
#define ADC_CCE_INT ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @brief adc flag
* @{
*/
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
#define ADC_CCE_FLAG ((uint8_t)0x02) /*!< channels conversion end flag */
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
/**
* @}
*/
/** @defgroup ADC_exported_types
* @{
*/
/**
* @brief adc data align type
*/
typedef enum
{
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
} adc_data_align_type;
/**
* @brief adc channel select type
*/
typedef enum
{
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
ADC_CHANNEL_17 = 0x11 /*!< adc channel 17 */
} adc_channel_select_type;
/**
* @brief adc sampletime select type
*/
typedef enum
{
ADC_SAMPLETIME_1_5 = 0x00, /*!< adc sample time 1.5 cycle */
ADC_SAMPLETIME_7_5 = 0x01, /*!< adc sample time 7.5 cycle */
ADC_SAMPLETIME_13_5 = 0x02, /*!< adc sample time 13.5 cycle */
ADC_SAMPLETIME_28_5 = 0x03, /*!< adc sample time 28.5 cycle */
ADC_SAMPLETIME_41_5 = 0x04, /*!< adc sample time 41.5 cycle */
ADC_SAMPLETIME_55_5 = 0x05, /*!< adc sample time 55.5 cycle */
ADC_SAMPLETIME_71_5 = 0x06, /*!< adc sample time 71.5 cycle */
ADC_SAMPLETIME_239_5 = 0x07 /*!< adc sample time 239.5 cycle */
} adc_sampletime_select_type;
/**
* @brief adc ordinary group trigger event select type
*/
typedef enum
{
/*adc1 ordinary trigger event*/
ADC12_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR3TRGOUT = 0x04, /*!< timer3 trgout event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_TMR15CH1 = 0x05, /*!< timer15 ch1 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_EXINT11 = 0x06, /*!< exint line11 event as trigger source of adc1 ordinary sequence */
ADC12_ORDINARY_TRIG_SOFTWARE = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc1 ordinary sequence */
} adc_ordinary_trig_select_type;
/**
* @brief adc preempt group trigger event select type
*/
typedef enum
{
/*adc1 preempt trigger event*/
ADC12_PREEMPT_TRIG_TMR1TRGOUT = 0x00, /*!< timer1 trgout event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR1CH4 = 0x01, /*!< timer1 ch4 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR3CH4 = 0x04, /*!< timer3 ch4 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_TMR15TRGOUT = 0x05, /*!< timer15 trgout event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_EXINT15 = 0x06, /*!< exint line15 event as trigger source of adc1 preempt sequence */
ADC12_PREEMPT_TRIG_SOFTWARE = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc1 preempt sequence */
} adc_preempt_trig_select_type;
/**
* @brief adc preempt channel type
*/
typedef enum
{
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
} adc_preempt_channel_type;
/**
* @brief adc voltage_monitoring type
*/
typedef enum
{
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
} adc_voltage_monitoring_type;
/**
* @brief adc base config type
*/
typedef struct
{
confirm_state sequence_mode; /*!< adc sequence mode */
confirm_state repeat_mode; /*!< adc repeat mode */
adc_data_align_type data_align; /*!< adc data alignment */
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
} adc_base_config_type;
/**
* @brief type define adc register all
*/
typedef struct
{
/**
* @brief adc sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t vmor : 1; /* [0] */
__IO uint32_t cce : 1; /* [1] */
__IO uint32_t pcce : 1; /* [2] */
__IO uint32_t pccs : 1; /* [3] */
__IO uint32_t occs : 1; /* [4] */
__IO uint32_t reserved1 : 27;/* [31:5] */
} sts_bit;
};
/**
* @brief adc ctrl1 register, offset:0x04
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t vmcsel : 5; /* [4:0] */
__IO uint32_t cceien : 1; /* [5] */
__IO uint32_t vmorien : 1; /* [6] */
__IO uint32_t pcceien : 1; /* [7] */
__IO uint32_t sqen : 1; /* [8] */
__IO uint32_t vmsgen : 1; /* [9] */
__IO uint32_t pcautoen : 1; /* [10] */
__IO uint32_t ocpen : 1; /* [11] */
__IO uint32_t pcpen : 1; /* [12] */
__IO uint32_t ocpcnt : 3; /* [15:13] */
__IO uint32_t reserved1 : 6; /* [21:16] */
__IO uint32_t pcvmen : 1; /* [22] */
__IO uint32_t ocvmen : 1; /* [23] */
__IO uint32_t reserved2 : 8; /* [31:24] */
} ctrl1_bit;
};
/**
* @brief adc ctrl2 register, offset:0x08
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t adcen : 1; /* [0] */
__IO uint32_t rpen : 1; /* [1] */
__IO uint32_t adcal : 1; /* [2] */
__IO uint32_t adcalinit : 1; /* [3] */
__IO uint32_t reserved1 : 4; /* [7:4] */
__IO uint32_t ocdmaen : 1; /* [8] */
__IO uint32_t reserved2 : 2; /* [10:9] */
__IO uint32_t dtalign : 1; /* [11] */
__IO uint32_t pctesel : 3; /* [14:12] */
__IO uint32_t pcten : 1; /* [15] */
__IO uint32_t reserved3 : 1; /* [16] */
__IO uint32_t octesel : 3; /* [19:17] */
__IO uint32_t octen : 1; /* [20] */
__IO uint32_t pcswtrg : 1; /* [21] */
__IO uint32_t ocswtrg : 1; /* [22] */
__IO uint32_t itsrven : 1; /* [23] */
__IO uint32_t reserved4 : 8; /* [31:24] */
} ctrl2_bit;
};
/**
* @brief adc spt1 register, offset:0x0C
*/
union
{
__IO uint32_t spt1;
struct
{
__IO uint32_t cspt10 : 3; /* [2:0] */
__IO uint32_t cspt11 : 3; /* [5:3] */
__IO uint32_t cspt12 : 3; /* [8:6] */
__IO uint32_t cspt13 : 3; /* [11:9] */
__IO uint32_t cspt14 : 3; /* [14:12] */
__IO uint32_t cspt15 : 3; /* [17:15] */
__IO uint32_t cspt16 : 3; /* [20:18] */
__IO uint32_t cspt17 : 3; /* [23:21] */
__IO uint32_t reserved1 : 8;/* [31:24] */
} spt1_bit;
};
/**
* @brief adc spt2 register, offset:0x10
*/
union
{
__IO uint32_t spt2;
struct
{
__IO uint32_t cspt0 : 3;/* [2:0] */
__IO uint32_t cspt1 : 3;/* [5:3] */
__IO uint32_t cspt2 : 3;/* [8:6] */
__IO uint32_t cspt3 : 3;/* [11:9] */
__IO uint32_t cspt4 : 3;/* [14:12] */
__IO uint32_t cspt5 : 3;/* [17:15] */
__IO uint32_t cspt6 : 3;/* [20:18] */
__IO uint32_t cspt7 : 3;/* [23:21] */
__IO uint32_t cspt8 : 3;/* [26:24] */
__IO uint32_t cspt9 : 3;/* [29:27] */
__IO uint32_t reserved1 : 2;/* [31:30] */
} spt2_bit;
};
/**
* @brief adc pcdto1 register, offset:0x14
*/
union
{
__IO uint32_t pcdto1;
struct
{
__IO uint32_t pcdto1 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto1_bit;
};
/**
* @brief adc pcdto2 register, offset:0x18
*/
union
{
__IO uint32_t pcdto2;
struct
{
__IO uint32_t pcdto2 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto2_bit;
};
/**
* @brief adc pcdto3 register, offset:0x1C
*/
union
{
__IO uint32_t pcdto3;
struct
{
__IO uint32_t pcdto3 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto3_bit;
};
/**
* @brief adc pcdto4 register, offset:0x20
*/
union
{
__IO uint32_t pcdto4;
struct
{
__IO uint32_t pcdto4 : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} pcdto4_bit;
};
/**
* @brief adc vmhb register, offset:0x24
*/
union
{
__IO uint32_t vmhb;
struct
{
__IO uint32_t vmhb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmhb_bit;
};
/**
* @brief adc vmlb register, offset:0x28
*/
union
{
__IO uint32_t vmlb;
struct
{
__IO uint32_t vmlb : 12; /* [11:0] */
__IO uint32_t reserved1 : 20; /* [31:12] */
} vmlb_bit;
};
/**
* @brief adc osq1 register, offset:0x2C
*/
union
{
__IO uint32_t osq1;
struct
{
__IO uint32_t osn13 : 5; /* [4:0] */
__IO uint32_t osn14 : 5; /* [9:5] */
__IO uint32_t osn15 : 5; /* [14:10] */
__IO uint32_t osn16 : 5; /* [19:15] */
__IO uint32_t oclen : 4; /* [23:20] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} osq1_bit;
};
/**
* @brief adc osq2 register, offset:0x30
*/
union
{
__IO uint32_t osq2;
struct
{
__IO uint32_t osn7 : 5; /* [4:0] */
__IO uint32_t osn8 : 5; /* [9:5] */
__IO uint32_t osn9 : 5; /* [14:10] */
__IO uint32_t osn10 : 5; /* [19:15] */
__IO uint32_t osn11 : 5; /* [24:20] */
__IO uint32_t osn12 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq2_bit;
};
/**
* @brief adc osq3 register, offset:0x34
*/
union
{
__IO uint32_t osq3;
struct
{
__IO uint32_t osn1 : 5; /* [4:0] */
__IO uint32_t osn2 : 5; /* [9:5] */
__IO uint32_t osn3 : 5; /* [14:10] */
__IO uint32_t osn4 : 5; /* [19:15] */
__IO uint32_t osn5 : 5; /* [24:20] */
__IO uint32_t osn6 : 5; /* [29:25] */
__IO uint32_t reserved1 : 2; /* [31:30] */
} osq3_bit;
};
/**
* @brief adc psq register, offset:0x38
*/
union
{
__IO uint32_t psq;
struct
{
__IO uint32_t psn1 : 5; /* [4:0] */
__IO uint32_t psn2 : 5; /* [9:5] */
__IO uint32_t psn3 : 5; /* [14:10] */
__IO uint32_t psn4 : 5; /* [19:15] */
__IO uint32_t pclen : 2; /* [21:20] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} psq_bit;
};
/**
* @brief adc pdt1 register, offset:0x3C
*/
union
{
__IO uint32_t pdt1;
struct
{
__IO uint32_t pdt1 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt1_bit;
};
/**
* @brief adc pdt2 register, offset:0x40
*/
union
{
__IO uint32_t pdt2;
struct
{
__IO uint32_t pdt2 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt2_bit;
};
/**
* @brief adc pdt3 register, offset:0x44
*/
union
{
__IO uint32_t pdt3;
struct
{
__IO uint32_t pdt3 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt3_bit;
};
/**
* @brief adc pdt4 register, offset:0x48
*/
union
{
__IO uint32_t pdt4;
struct
{
__IO uint32_t pdt4 : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} pdt4_bit;
};
/**
* @brief adc odt register, offset:0x4C
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt : 16; /* [15:0] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} odt_bit;
};
} adc_type;
/**
* @}
*/
#define ADC1 ((adc_type *) ADC1_BASE)
/** @defgroup ADC_exported_functions
* @{
*/
void adc_reset(adc_type *adc_x);
void adc_enable(adc_type *adc_x, confirm_state new_state);
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
void adc_calibration_init(adc_type *adc_x);
flag_status adc_calibration_init_status_get(adc_type *adc_x);
void adc_calibration_start(adc_type *adc_x);
flag_status adc_calibration_status_get(adc_type *adc_x);
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state);
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state);
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_tempersensor_vintrv_enable(confirm_state new_state);
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_cmp.h
+279
View File
@@ -0,0 +1,279 @@
/**
**************************************************************************
* @file at32f421_cmp.h
* @brief at32f421 cmp header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_CMP_H
#define __AT32F421_CMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup CMP
* @{
*/
/** @defgroup CMP_exported_types
* @{
*/
/**
* @brief cmp non-inverting type
*/
typedef enum
{
CMP_NON_INVERTING_PA5 = 0x00, /*!< comparator non-inverting connect to pa5 */
CMP_NON_INVERTING_PA1 = 0x01, /*!< comparator non-inverting connect to pa1 */
CMP_NON_INVERTING_PA0 = 0x02, /*!< comparator non-inverting connect to pa0 */
CMP_NON_INVERTING_VSSA = 0x03 /*!< comparator non-inverting connect to vssa */
} cmp_non_inverting_type;
/**
* @brief cmp inverting type
*/
typedef enum
{
CMP_INVERTING_1_4VREFINT = 0x00, /*!< comparator inverting connect to 1_4vrefint */
CMP_INVERTING_1_2VREFINT = 0x01, /*!< comparator inverting connect to 1_2vrefint */
CMP_INVERTING_3_4VREFINT = 0x02, /*!< comparator inverting connect to 3_4vrefint */
CMP_INVERTING_VREFINT = 0x03, /*!< comparator inverting connect to vrefint */
CMP_INVERTING_PA4 = 0x04, /*!< comparator inverting connect to pa4 */
CMP_INVERTING_PA5 = 0x05, /*!< comparator inverting connect to pa5 */
CMP_INVERTING_PA0 = 0x06, /*!< comparator inverting connect to pa0 */
CMP_INVERTING_PA2 = 0x07 /*!< comparator inverting connect to pa2 */
} cmp_inverting_type;
/**
* @brief cmp speed type
*/
typedef enum
{
CMP_SPEED_FAST = 0x00, /*!< comparator selected fast speed */
CMP_SPEED_MEDIUM = 0x01, /*!< comparator selected medium speed */
CMP_SPEED_SLOW = 0x02, /*!< comparator selected slow speed */
CMP_SPEED_ULTRALOW = 0x03 /*!< comparator selected ultralow speed */
} cmp_speed_type;
#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR
#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR
/**
* @brief cmp output type
*/
typedef enum
{
CMP_OUTPUT_NONE = 0x00, /*!< comparator has no output */
CMP_OUTPUT_TMR1BRK = 0x01, /*!< comparator output connect to tmr1brk */
CMP_OUTPUT_TMR1CH1 = 0x02, /*!< comparator output connect to tmr1ch1 */
CMP_OUTPUT_TMR1CHCLR = 0x03, /*!< comparator output connect to tmr1chclr */
CMP_OUTPUT_TMR3CH1 = 0x06, /*!< comparator output connect to tmr3ch1 */
CMP_OUTPUT_TMR3CHCLR = 0x07 /*!< comparator output connect to tmr3chclr */
} cmp_output_type;
/**
* @brief cmp polarity type
*/
typedef enum
{
CMP_POL_NON_INVERTING = 0x00, /*!< comparator polarity non-inverting */
CMP_POL_INVERTING = 0x01, /*!< comparator polarity inverting */
} cmp_polarity_type;
/**
* @brief cmp hysteresis type
*/
typedef enum
{
CMP_HYSTERESIS_NONE = 0x00, /*!< comparator selected no hysteresis */
CMP_HYSTERESIS_LOW = 0x01, /*!< comparator selected low hysteresis */
CMP_HYSTERESIS_MEDIUM = 0x02, /*!< comparator selected medium hysteresis */
CMP_HYSTERESIS_HIGH = 0x03 /*!< comparator selected high hysteresis */
} cmp_hysteresis_type;
/**
* @brief cmp blanking type
*/
typedef enum
{
CMP_BLANKING_NONE = 0x00, /*!< comparator no blanking */
CMP_BLANKING_TMR1_CH4 = 0x01, /*!< comparator selected tmr1 ch4 as blanking */
CMP_BLANKING_TMR3_CH3 = 0x03, /*!< comparator selected tmr3 ch3 as blanking */
CMP_BLANKING_TMR15_CH2 = 0x04, /*!< comparator selected tmr15 ch2 as blanking */
CMP_BLANKING_TMR15_CH1 = 0x06 /*!< comparator selected tmr15 ch1 as blanking */
} cmp_blanking_type;
/**
* @brief cmp scale voltage and voltage bridge type
*/
typedef enum
{
CMP_SCAL_BRG_00 = 0x00, /*!< comparator selected vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 0v */
CMP_SCAL_BRG_10 = 0x02, /*!< comparator selected vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 1.2v */
CMP_SCAL_BRG_11 = 0x03 /*!< comparator selected vrefint = 1.2v, 3/4 vrefint = 0.9v, 1/2 vrefint = 0.6v, 1/4 vrefint = 0.3v */
} cmp_scal_brg_type;
/**
* @brief cmp selection type
*/
typedef enum
{
CMP1_SELECTION = 0x00, /*!< select comparator 1 */
} cmp_sel_type;
/**
* @brief cmp init type
*/
typedef struct
{
cmp_non_inverting_type cmp_non_inverting; /*!< comparator non-inverting input selection */
cmp_inverting_type cmp_inverting; /*!< comparator inverting selection */
cmp_speed_type cmp_speed; /*!< comparator speed selection */
cmp_output_type cmp_output; /*!< comparator output target selection */
cmp_polarity_type cmp_polarity; /*!< comparator polarity selection */
cmp_hysteresis_type cmp_hysteresis; /*!< comparator hysteresis selection */
}cmp_init_type;
/**
* @brief type define cmp register all
*/
typedef struct
{
/**
* @brief cmp control and status register, offset:0x1C
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t cmpen : 1; /* [0] */
__IO uint32_t cmpis : 1; /* [1] */
__IO uint32_t cmpssel : 2; /* [3:2] */
__IO uint32_t cmpinvsel : 3; /* [6:4] */
__IO uint32_t cmpninvsel : 2; /* [8:7] */
__IO uint32_t reserved1 : 1; /* [9] */
__IO uint32_t cmptag : 3; /* [12:10] */
__IO uint32_t reserved2 : 2; /* [14:13] */
__IO uint32_t cmpp : 1; /* [15] */
__IO uint32_t cmphyst : 2; /* [17:16] */
__IO uint32_t cmpblanking : 3; /* [20:18] */
__IO uint32_t reserved3 : 1; /* [21] */
__IO uint32_t brgen : 1; /* [22] */
__IO uint32_t scalen : 1; /* [23] */
__IO uint32_t reserved4 : 6; /* [29:24] */
__IO uint32_t cmpvalue : 1; /* [30] */
__IO uint32_t cmpwp : 1; /* [31] */
} ctrlsts_bit;
};
/**
* @brief crm reserved1 register, offset:0x20
*/
__IO uint32_t reserved1;
/**
* @brief cmp Glitch filter enable register, offset:0x24
*/
union
{
__IO uint32_t g_filter_en;
struct
{
__IO uint32_t gfe : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} g_filter_en_bit;
};
/**
* @brief cmp high pulse count register, offset:0x28
*/
union
{
__IO uint32_t high_pulse;
struct
{
__IO uint32_t h_pulse_cnt : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} high_pulse_bit;
};
/**
* @brief cmp low pulse count register, offset:0x2C
*/
union
{
__IO uint32_t low_pulse;
struct
{
__IO uint32_t l_pulse_cnt : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} low_pulse_bit;
};
} cmp_type;
/**
* @}
*/
#define CMP ((cmp_type *) (SCFG_CMP_BASE + 0x1C))
/** @defgroup CMP_exported_functions
* @{
*/
void cmp_reset(void);
void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct);
void cmp_default_para_init(cmp_init_type *cmp_init_struct);
void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state);
void cmp_input_shift_enable(confirm_state new_state);
uint32_t cmp_output_value_get(cmp_sel_type cmp_sel);
void cmp_write_protect_enable(cmp_sel_type cmp_sel);
void cmp_filter_config(uint16_t high_pulse_cnt, uint16_t low_pulse_cnt, confirm_state new_state);
void cmp_blanking_config(cmp_blanking_type blank_sel);
void cmp_scal_brg_config(cmp_scal_brg_type scal_brg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_crc.h
+198
View File
@@ -0,0 +1,198 @@
/**
**************************************************************************
* @file at32f421_crc.h
* @brief at32f421 crc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_CRC_H
#define __AT32F421_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_exported_types
* @{
*/
/**
* @brief crc reverse input data
*/
typedef enum
{
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
} crc_reverse_input_type;
/**
* @brief crc reverse output data
*/
typedef enum
{
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
typedef struct
{
/**
* @brief crc dt register, offset:0x00
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 32; /* [31:0] */
} dt_bit;
};
/**
* @brief crc cdt register, offset:0x04
*/
union
{
__IO uint32_t cdt;
struct
{
__IO uint32_t cdt : 8 ; /* [7:0] */
__IO uint32_t reserved1 : 24 ;/* [31:8] */
} cdt_bit;
};
/**
* @brief crc ctrl register, offset:0x08
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
} ctrl_bit;
};
/**
* @brief crm reserved1 register, offset:0x0C
*/
__IO uint32_t reserved1;
/**
* @brief crc idt register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt : 32; /* [31:0] */
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
* @}
*/
#define CRC ((crc_type *) CRC_BASE)
/** @defgroup CRC_exported_functions
* @{
*/
void crc_data_reset(void);
uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_crm.h
+837
View File
@@ -0,0 +1,837 @@
/**
**************************************************************************
* @file at32f421_crm.h
* @brief at32f421 crm header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_CRM_H
#define __AT32F421_CRM_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup CRM
* @{
*/
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
/** @defgroup CRM_flags_definition
* @brief crm flag
* @{
*/
#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x20, 1) /*!< low speed external crystal stable flag */
#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x24, 1) /*!< low speed internal clock stable flag */
#define CRM_ALL_RESET_FLAG MAKE_VALUE(0x24, 24) /*!< all reset flag */
#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x24, 26) /*!< nrst pin reset flag */
#define CRM_POR_RESET_FLAG MAKE_VALUE(0x24, 27) /*!< power on reset flag */
#define CRM_SW_RESET_FLAG MAKE_VALUE(0x24, 28) /*!< software reset flag */
#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x24, 29) /*!< watchdog timer reset flag */
#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x24, 30) /*!< window watchdog timer reset flag */
#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x24, 31) /*!< low-power reset flag */
#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x08, 0) /*!< low speed internal clock stable interrupt ready flag */
#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x08, 1) /*!< low speed external crystal stable interrupt ready flag */
#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x08, 2) /*!< high speed internal clock stable interrupt ready flag */
#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x08, 3) /*!< high speed external crystal stable interrupt ready flag */
#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x08, 4) /*!< phase locking loop stable interrupt ready flag */
#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x08, 7) /*!< clock failure interrupt ready flag */
/**
* @}
*/
/** @defgroup CRM_interrupts_definition
* @brief crm interrupt
* @{
*/
#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
/**
* @}
*/
/** @defgroup CRM_exported_types
* @{
*/
/**
* @brief crm periph clock
*/
typedef enum
{
/* ahb periph */
CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x14, 0), /*!< dma1 periph clock */
CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x14, 6), /*!< crc periph clock */
CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x14, 17), /*!< gpioa periph clock */
CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x14, 18), /*!< gpiob periph clock */
CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x14, 19), /*!< gpioc periph clock */
CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x14, 22), /*!< gpiof periph clock */
/* apb2 periph */
CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x18, 0), /*!< scfg periph clock */
CRM_CMP_PERIPH_CLOCK = MAKE_VALUE(0x18, 0), /*!< comparator periph clock */
CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x18, 9), /*!< adc1 periph clock */
CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x18, 11), /*!< tmr1 periph clock */
CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x18, 12), /*!< spi1 periph clock */
CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x18, 14), /*!< usart1 periph clock */
CRM_TMR15_PERIPH_CLOCK = MAKE_VALUE(0x18, 16), /*!< tmr15 periph clock */
CRM_TMR16_PERIPH_CLOCK = MAKE_VALUE(0x18, 17), /*!< tmr16 periph clock */
CRM_TMR17_PERIPH_CLOCK = MAKE_VALUE(0x18, 18), /*!< tmr17 periph clock */
/* apb1 periph */
CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x1C, 1), /*!< tmr3 periph clock */
CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x1C, 4), /*!< tmr6 periph clock */
CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x1C, 8), /*!< tmr14 periph clock */
CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x1C, 11), /*!< wwdt periph clock */
CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 14), /*!< spi2 periph clock */
CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */
CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */
CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */
CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */
} crm_periph_clock_type;
/**
* @brief crm periph reset
*/
typedef enum
{
/* ahb periph */
CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x28, 17), /*!< gpioa periph reset */
CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x28, 18), /*!< gpiob periph reset */
CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x28, 19), /*!< gpioc periph reset */
CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x28, 22), /*!< gpiof periph reset */
/* apb2 periph */
CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x0C, 0), /*!< scfg periph reset */
CRM_CMP_PERIPH_RESET = MAKE_VALUE(0x0C, 0), /*!< comparator periph reset */
CRM_EXINT_PERIPH_RESET = MAKE_VALUE(0x0C, 1), /*!< exint periph reset */
CRM_ADC1_PERIPH_RESET = MAKE_VALUE(0x0C, 9), /*!< adc1 periph reset */
CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x0C, 11), /*!< tmr1 periph reset */
CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x0C, 12), /*!< spi2 periph reset */
CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x0C, 14), /*!< usart1 periph reset */
CRM_TMR15_PERIPH_RESET = MAKE_VALUE(0x0C, 16), /*!< tmr15 periph reset */
CRM_TMR16_PERIPH_RESET = MAKE_VALUE(0x0C, 17), /*!< tmr16 periph reset */
CRM_TMR17_PERIPH_RESET = MAKE_VALUE(0x0C, 18), /*!< tmr17 periph reset */
/* apb1 periph */
CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< tmr3 periph reset */
CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< tmr6 periph reset */
CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x10, 8), /*!< tmr14 periph reset */
CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x10, 11), /*!< wwdt periph reset */
CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x10, 14), /*!< spi2 periph reset */
CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */
CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */
CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */
CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */
} crm_periph_reset_type;
/**
* @brief crm periph clock in sleep mode
*/
typedef enum
{
/* ahb periph */
CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 2), /*!< sram sleep mode periph clock */
CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE = MAKE_VALUE(0x14, 4) /*!< flash sleep mode periph clock */
} crm_periph_clock_sleepmd_type;
/**
* @brief crm pll mult_x
*/
typedef enum
{
CRM_PLL_MULT_2 = 0, /*!< pll multiplication factor 2 */
CRM_PLL_MULT_3 = 1, /*!< pll multiplication factor 3 */
CRM_PLL_MULT_4 = 2, /*!< pll multiplication factor 4 */
CRM_PLL_MULT_5 = 3, /*!< pll multiplication factor 5 */
CRM_PLL_MULT_6 = 4, /*!< pll multiplication factor 6 */
CRM_PLL_MULT_7 = 5, /*!< pll multiplication factor 7 */
CRM_PLL_MULT_8 = 6, /*!< pll multiplication factor 8 */
CRM_PLL_MULT_9 = 7, /*!< pll multiplication factor 9 */
CRM_PLL_MULT_10 = 8, /*!< pll multiplication factor 10 */
CRM_PLL_MULT_11 = 9, /*!< pll multiplication factor 11 */
CRM_PLL_MULT_12 = 10, /*!< pll multiplication factor 12 */
CRM_PLL_MULT_13 = 11, /*!< pll multiplication factor 13 */
CRM_PLL_MULT_14 = 12, /*!< pll multiplication factor 14 */
CRM_PLL_MULT_15 = 13, /*!< pll multiplication factor 15 */
CRM_PLL_MULT_16 = 15, /*!< pll multiplication factor 16 */
CRM_PLL_MULT_17 = 16, /*!< pll multiplication factor 17 */
CRM_PLL_MULT_18 = 17, /*!< pll multiplication factor 18 */
CRM_PLL_MULT_19 = 18, /*!< pll multiplication factor 19 */
CRM_PLL_MULT_20 = 19, /*!< pll multiplication factor 20 */
CRM_PLL_MULT_21 = 20, /*!< pll multiplication factor 21 */
CRM_PLL_MULT_22 = 21, /*!< pll multiplication factor 22 */
CRM_PLL_MULT_23 = 22, /*!< pll multiplication factor 23 */
CRM_PLL_MULT_24 = 23, /*!< pll multiplication factor 24 */
CRM_PLL_MULT_25 = 24, /*!< pll multiplication factor 25 */
CRM_PLL_MULT_26 = 25, /*!< pll multiplication factor 26 */
CRM_PLL_MULT_27 = 26, /*!< pll multiplication factor 27 */
CRM_PLL_MULT_28 = 27, /*!< pll multiplication factor 28 */
CRM_PLL_MULT_29 = 28, /*!< pll multiplication factor 29 */
CRM_PLL_MULT_30 = 29, /*!< pll multiplication factor 30 */
CRM_PLL_MULT_31 = 30, /*!< pll multiplication factor 31 */
CRM_PLL_MULT_32 = 31, /*!< pll multiplication factor 32 */
CRM_PLL_MULT_33 = 32, /*!< pll multiplication factor 33 */
CRM_PLL_MULT_34 = 33, /*!< pll multiplication factor 34 */
CRM_PLL_MULT_35 = 34, /*!< pll multiplication factor 35 */
CRM_PLL_MULT_36 = 35, /*!< pll multiplication factor 36 */
CRM_PLL_MULT_37 = 36, /*!< pll multiplication factor 37 */
CRM_PLL_MULT_38 = 37, /*!< pll multiplication factor 38 */
CRM_PLL_MULT_39 = 38, /*!< pll multiplication factor 39 */
CRM_PLL_MULT_40 = 39, /*!< pll multiplication factor 40 */
CRM_PLL_MULT_41 = 40, /*!< pll multiplication factor 41 */
CRM_PLL_MULT_42 = 41, /*!< pll multiplication factor 42 */
CRM_PLL_MULT_43 = 42, /*!< pll multiplication factor 43 */
CRM_PLL_MULT_44 = 43, /*!< pll multiplication factor 44 */
CRM_PLL_MULT_45 = 44, /*!< pll multiplication factor 45 */
CRM_PLL_MULT_46 = 45, /*!< pll multiplication factor 46 */
CRM_PLL_MULT_47 = 46, /*!< pll multiplication factor 47 */
CRM_PLL_MULT_48 = 47, /*!< pll multiplication factor 48 */
CRM_PLL_MULT_49 = 48, /*!< pll multiplication factor 49 */
CRM_PLL_MULT_50 = 49, /*!< pll multiplication factor 50 */
CRM_PLL_MULT_51 = 50, /*!< pll multiplication factor 51 */
CRM_PLL_MULT_52 = 51, /*!< pll multiplication factor 52 */
CRM_PLL_MULT_53 = 52, /*!< pll multiplication factor 53 */
CRM_PLL_MULT_54 = 53, /*!< pll multiplication factor 54 */
CRM_PLL_MULT_55 = 54, /*!< pll multiplication factor 55 */
CRM_PLL_MULT_56 = 55, /*!< pll multiplication factor 56 */
CRM_PLL_MULT_57 = 56, /*!< pll multiplication factor 57 */
CRM_PLL_MULT_58 = 57, /*!< pll multiplication factor 58 */
CRM_PLL_MULT_59 = 58, /*!< pll multiplication factor 59 */
CRM_PLL_MULT_60 = 59, /*!< pll multiplication factor 60 */
CRM_PLL_MULT_61 = 60, /*!< pll multiplication factor 61 */
CRM_PLL_MULT_62 = 61, /*!< pll multiplication factor 62 */
CRM_PLL_MULT_63 = 62, /*!< pll multiplication factor 63 */
CRM_PLL_MULT_64 = 63 /*!< pll multiplication factor 64 */
} crm_pll_mult_type;
/**
* @brief crm pll fref_x
*/
typedef enum
{
CRM_PLL_FREF_4M = 0, /*!< pll refrence clock between 3.9 mhz and 5 mhz */
CRM_PLL_FREF_6M = 1, /*!< pll refrence clock between 5.2 mhz and 6.25 mhz */
CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */
CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */
CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */
CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */
} crm_pll_fref_type;
/**
* @brief crm pll clock source
*/
typedef enum
{
CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
CRM_PLL_SOURCE_HEXT = 0x01, /*!< high speed external crystal as pll reference clock source */
CRM_PLL_SOURCE_HEXT_DIV = 0x02 /*!< high speed external crystal div as pll reference clock source */
} crm_pll_clock_source_type;
/**
* @brief crm pll fr
*/
typedef enum
{
CRM_PLL_FR_1 = 0x00, /*!< pll post-division div1 */
CRM_PLL_FR_2 = 0x01, /*!< pll post-division div2 */
CRM_PLL_FR_4 = 0x02, /*!< pll post-division div4 */
CRM_PLL_FR_8 = 0x03, /*!< pll post-division div8 */
CRM_PLL_FR_16 = 0x04, /*!< pll post-division div16 */
CRM_PLL_FR_32 = 0x05 /*!< pll post-division div32 */
} crm_pll_fr_type;
/**
* @brief crm clock source
*/
typedef enum
{
CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
} crm_clock_source_type;
/**
* @brief crm ahb division
*/
typedef enum
{
CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
} crm_ahb_div_type;
/**
* @brief crm apb1 division
*/
typedef enum
{
CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
} crm_apb1_div_type;
/**
* @brief crm apb2 division
*/
typedef enum
{
CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
} crm_apb2_div_type;
/**
* @brief crm adc division
*/
typedef enum
{
CRM_ADC_DIV_2 = 0x00, /*!< apb2clk div2 to adcclk */
CRM_ADC_DIV_4 = 0x01, /*!< apb2clk div4 to adcclk */
CRM_ADC_DIV_6 = 0x02, /*!< apb2clk div6 to adcclk */
CRM_ADC_DIV_8 = 0x03, /*!< apb2clk div8 to adcclk */
CRM_ADC_DIV_12 = 0x05, /*!< apb2clk div12 to adcclk */
CRM_ADC_DIV_16 = 0x07 /*!< apb2clk div16 to adcclk */
} crm_adc_div_type;
/**
* @brief crm ertc clock
*/
typedef enum
{
CRM_ERTC_CLOCK_NOCLK = 0x00, /*!< no clock as ertc clock source */
CRM_ERTC_CLOCK_LEXT = 0x01, /*!< low speed external crystal as ertc clock source */
CRM_ERTC_CLOCK_LICK = 0x02, /*!< low speed internal clock as ertc clock source */
CRM_ERTC_CLOCK_HEXT_DIV = 0x03 /*!< high speed external crystal div as ertc clock source */
} crm_ertc_clock_type;
/**
* @brief crm hick 48mhz division
*/
typedef enum
{
CRM_HICK48_DIV6 = 0x00, /*!< high speed internal clock (48 mhz) div6 */
CRM_HICK48_NODIV = 0x01 /*!< high speed internal clock (48 mhz) no div */
} crm_hick_div_6_type;
/**
* @brief crm sclk select
*/
typedef enum
{
CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
} crm_sclk_type;
/**
* @brief crm clkout select
*/
typedef enum
{
CRM_CLKOUT_NOCLK = 0x00, /*!< output no clock to clkout pin */
CRM_CLKOUT_LICK = 0x02, /*!< output low speed internal clock to clkout pin */
CRM_CLKOUT_LEXT = 0x03, /*!< output low speed external crystal to clkout pin */
CRM_CLKOUT_SCLK = 0x04, /*!< output system clock to clkout pin */
CRM_CLKOUT_HICK = 0x05, /*!< output high speed internal clock to clkout pin */
CRM_CLKOUT_HEXT = 0x06, /*!< output high speed external crystal to clkout pin */
CRM_CLKOUT_PLL_DIV_2 = 0x07, /*!< output phase locking loop clock div2 to clkout pin */
CRM_CLKOUT_PLL_DIV_4 = 0x0C, /*!< output phase locking loop clock div4 to clkout pin */
CRM_CLKOUT_ADC = 0x0E /*!< output adcclk to clkout pin */
} crm_clkout_select_type;
/**
* @brief crm clkout division
*/
typedef enum
{
CRM_CLKOUT_DIV_1 = 0x00, /*!< clkout div1 */
CRM_CLKOUT_DIV_2 = 0x08, /*!< clkout div2 */
CRM_CLKOUT_DIV_4 = 0x09, /*!< clkout div4 */
CRM_CLKOUT_DIV_8 = 0x0A, /*!< clkout div8 */
CRM_CLKOUT_DIV_16 = 0x0B, /*!< clkout div16 */
CRM_CLKOUT_DIV_64 = 0x0C, /*!< clkout div64 */
CRM_CLKOUT_DIV_128 = 0x0D, /*!< clkout div128 */
CRM_CLKOUT_DIV_256 = 0x0E, /*!< clkout div256 */
CRM_CLKOUT_DIV_512 = 0x0F /*!< clkout div512 */
} crm_clkout_div_type;
/**
* @brief crm auto step mode
*/
typedef enum
{
CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
} crm_auto_step_mode_type;
/**
* @brief crm hick as system clock frequency select
*/
typedef enum
{
CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
} crm_hick_sclk_frequency_type;
/**
* @brief crm clocks freqency structure
*/
typedef struct
{
uint32_t sclk_freq; /*!< system clock frequency */
uint32_t ahb_freq; /*!< ahb bus clock frequency */
uint32_t apb2_freq; /*!< apb2 bus clock frequency */
uint32_t apb1_freq; /*!< apb1 bus clock frequency */
uint32_t adc_freq; /*!< adc clock frequency */
} crm_clocks_freq_type;
/**
* @brief type define crm register all
*/
typedef struct
{
/**
* @brief crm ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t hicken : 1; /* [0] */
__IO uint32_t hickstbl : 1; /* [1] */
__IO uint32_t hicktrim : 6; /* [7:2] */
__IO uint32_t hickcal : 8; /* [15:8] */
__IO uint32_t hexten : 1; /* [16] */
__IO uint32_t hextstbl : 1; /* [17] */
__IO uint32_t hextbyps : 1; /* [18] */
__IO uint32_t cfden : 1; /* [19] */
__IO uint32_t reserved1 : 4; /* [23:20] */
__IO uint32_t pllen : 1; /* [24] */
__IO uint32_t pllstbl : 1; /* [25] */
__IO uint32_t reserved2 : 6; /* [31:26] */
} ctrl_bit;
};
/**
* @brief crm cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t sclksel : 2; /* [1:0] */
__IO uint32_t sclksts : 2; /* [3:2] */
__IO uint32_t ahbdiv : 4; /* [7:4] */
__IO uint32_t apb1div : 3; /* [10:8] */
__IO uint32_t apb2div : 3; /* [13:11] */
__IO uint32_t adcdiv_l : 2; /* [15:14] */
__IO uint32_t pllrcs : 1; /* [16] */
__IO uint32_t pllhextdiv : 1; /* [17] */
__IO uint32_t pllmult_l : 4; /* [21:18] */
__IO uint32_t reserved1 : 2; /* [23:22] */
__IO uint32_t clkout_sel : 3; /* [26:24] */
__IO uint32_t reserved2 : 1; /* [27] */
__IO uint32_t adcdiv_h : 1; /* [28] */
__IO uint32_t pllmult_h : 2; /* [30:29] */
__IO uint32_t reserved3 : 1; /* [31] */
} cfg_bit;
};
/**
* @brief crm clkint register, offset:0x08
*/
union
{
__IO uint32_t clkint;
struct
{
__IO uint32_t lickstblf : 1; /* [0] */
__IO uint32_t lextstblf : 1; /* [1] */
__IO uint32_t hickstblf : 1; /* [2] */
__IO uint32_t hextstblf : 1; /* [3] */
__IO uint32_t pllstblf : 1; /* [4] */
__IO uint32_t reserved1 : 2; /* [6:5] */
__IO uint32_t cfdf : 1; /* [7] */
__IO uint32_t lickstblien : 1; /* [8] */
__IO uint32_t lextstblien : 1; /* [9] */
__IO uint32_t hickstblien : 1; /* [10] */
__IO uint32_t hextstblien : 1; /* [11] */
__IO uint32_t pllstblien : 1; /* [12] */
__IO uint32_t reserved2 : 3; /* [15:13] */
__IO uint32_t lickstblfc : 1; /* [16] */
__IO uint32_t lextstblfc : 1; /* [17] */
__IO uint32_t hickstblfc : 1; /* [18] */
__IO uint32_t hextstblfc : 1; /* [19] */
__IO uint32_t pllstblfc : 1; /* [20] */
__IO uint32_t reserved3 : 2; /* [22:21] */
__IO uint32_t cfdfc : 1; /* [23] */
__IO uint32_t reserved4 : 8; /* [31:24] */
} clkint_bit;
};
/**
* @brief crm apb2rst register, offset:0x0C
*/
union
{
__IO uint32_t apb2rst;
struct
{
__IO uint32_t scfgcmprst : 1; /* [0] */
__IO uint32_t exintrst : 1; /* [1] */
__IO uint32_t reserved1 : 7; /* [8:2] */
__IO uint32_t adc1rst : 1; /* [9] */
__IO uint32_t reserved2 : 1; /* [10] */
__IO uint32_t tmr1rst : 1; /* [11] */
__IO uint32_t spi1rst : 1; /* [12] */
__IO uint32_t reserved3 : 1; /* [13] */
__IO uint32_t usart1rst : 1; /* [14] */
__IO uint32_t reserved4 : 1; /* [15] */
__IO uint32_t tmr15rst : 1; /* [16] */
__IO uint32_t tmr16rst : 1; /* [17] */
__IO uint32_t tmr17rst : 1; /* [18] */
__IO uint32_t reserved5 : 13;/* [31:19] */
} apb2rst_bit;
};
/**
* @brief crm apb1rst register, offset:0x10
*/
union
{
__IO uint32_t apb1rst;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t tmr3rst : 1; /* [1] */
__IO uint32_t reserved2 : 2; /* [3:2] */
__IO uint32_t tmr6rst : 1; /* [4] */
__IO uint32_t reserved3 : 3; /* [7:5] */
__IO uint32_t tmr14rst : 1; /* [8] */
__IO uint32_t reserved4 : 2; /* [10:9] */
__IO uint32_t wwdtrst : 1; /* [11] */
__IO uint32_t reserved5 : 2; /* [13:12] */
__IO uint32_t spi2rst : 1; /* [14] */
__IO uint32_t reserved6 : 2; /* [16:15] */
__IO uint32_t usart2rst : 1; /* [17] */
__IO uint32_t reserved7 : 3; /* [20:18] */
__IO uint32_t i2c1rst : 1; /* [21] */
__IO uint32_t i2c2rst : 1; /* [22] */
__IO uint32_t reserved8 : 5; /* [27:23] */
__IO uint32_t pwcrst : 1; /* [28] */
__IO uint32_t reserved9 : 3; /* [31:29] */
} apb1rst_bit;
};
/**
* @brief crm ahben register, offset:0x14
*/
union
{
__IO uint32_t ahben;
struct
{
__IO uint32_t dma1en : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t sramen : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t flashen : 1; /* [4] */
__IO uint32_t reserved3 : 1; /* [5] */
__IO uint32_t crcen : 1; /* [6] */
__IO uint32_t reserved4 : 10;/* [16:7] */
__IO uint32_t gpioaen : 1; /* [17] */
__IO uint32_t gpioben : 1; /* [18] */
__IO uint32_t gpiocen : 1; /* [19] */
__IO uint32_t reserved5 : 2; /* [21:20] */
__IO uint32_t gpiofen : 1; /* [22] */
__IO uint32_t reserved6 : 9; /* [31:23] */
} ahben_bit;
};
/**
* @brief crm apb2en register, offset:0x18
*/
union
{
__IO uint32_t apb2en;
struct
{
__IO uint32_t scfgcmpen : 1; /* [0] */
__IO uint32_t reserved1 : 8; /* [8:1] */
__IO uint32_t adc1en : 1; /* [9] */
__IO uint32_t reserved2 : 1; /* [10] */
__IO uint32_t tmr1en : 1; /* [11] */
__IO uint32_t spi1en : 1; /* [12] */
__IO uint32_t reserved3 : 1; /* [13] */
__IO uint32_t usart1en : 1; /* [14] */
__IO uint32_t reserved4 : 1; /* [15] */
__IO uint32_t tmr15en : 1; /* [16] */
__IO uint32_t tmr16en : 1; /* [17] */
__IO uint32_t tmr17en : 1; /* [18] */
__IO uint32_t reserved5 : 13;/* [31:19] */
} apb2en_bit;
};
/**
* @brief crm apb1en register, offset:0x1C
*/
union
{
__IO uint32_t apb1en;
struct
{
__IO uint32_t reserved1 : 1; /* [0] */
__IO uint32_t tmr3en : 1; /* [1] */
__IO uint32_t reserved2 : 2; /* [3:2] */
__IO uint32_t tmr6en : 1; /* [4] */
__IO uint32_t reserved3 : 3; /* [7:5] */
__IO uint32_t tmr14en : 1; /* [8] */
__IO uint32_t reserved4 : 2; /* [10:9] */
__IO uint32_t wwdten : 1; /* [11] */
__IO uint32_t reserved5 : 2; /* [13:12] */
__IO uint32_t spi2en : 1; /* [14] */
__IO uint32_t reserved6 : 2; /* [16:15] */
__IO uint32_t usart2en : 1; /* [17] */
__IO uint32_t reserved7 : 3; /* [20:18] */
__IO uint32_t i2c1en : 1; /* [21] */
__IO uint32_t i2c2en : 1; /* [22] */
__IO uint32_t reserved8 : 5; /* [27:23] */
__IO uint32_t pwcen : 1; /* [28] */
__IO uint32_t reserved9 : 3; /* [31:29] */
} apb1en_bit;
};
/**
* @brief crm bpdc register, offset:0x20
*/
union
{
__IO uint32_t bpdc;
struct
{
__IO uint32_t lexten : 1; /* [0] */
__IO uint32_t lextstbl : 1; /* [1] */
__IO uint32_t lextbyps : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t ertcsel : 2; /* [9:8] */
__IO uint32_t reserved2 : 5; /* [14:10] */
__IO uint32_t ertcen : 1; /* [15] */
__IO uint32_t bpdrst : 1; /* [16] */
__IO uint32_t reserved3 : 15;/* [31:17] */
} bpdc_bit;
};
/**
* @brief crm ctrlsts register, offset:0x24
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t licken : 1; /* [0] */
__IO uint32_t lickstbl : 1; /* [1] */
__IO uint32_t reserved1 : 22;/* [23:2] */
__IO uint32_t rstfc : 1; /* [24] */
__IO uint32_t reserved2 : 1; /* [25] */
__IO uint32_t nrstf : 1; /* [26] */
__IO uint32_t porrstf : 1; /* [27] */
__IO uint32_t swrstf : 1; /* [28] */
__IO uint32_t wdtrstf : 1; /* [29] */
__IO uint32_t wwdtrstf : 1; /* [30] */
__IO uint32_t lprstf : 1; /* [31] */
} ctrlsts_bit;
};
/**
* @brief crm ahbrst register, offset:0x28
*/
union
{
__IO uint32_t ahbrst;
struct
{
__IO uint32_t reserved1 : 17;/* [16:0] */
__IO uint32_t gpioarst : 1; /* [17] */
__IO uint32_t gpiobrst : 1; /* [18] */
__IO uint32_t gpiocrst : 1; /* [19] */
__IO uint32_t reserved2 : 2; /* [21:20] */
__IO uint32_t gpiofrst : 1; /* [22] */
__IO uint32_t reserved3 : 9; /* [31:23] */
} ahbrst_bit;
};
/**
* @brief crm pll register, offset:0x2C
*/
union
{
__IO uint32_t pll;
struct
{
__IO uint32_t pllfr : 3; /* [2:0] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t pllms : 4; /* [7:4] */
__IO uint32_t pllns : 9; /* [16:8] */
__IO uint32_t reserved2 : 7; /* [23:17] */
__IO uint32_t pllfref : 3; /* [26:24] */
__IO uint32_t reserved3 : 4; /* [30:27] */
__IO uint32_t pllcfgen : 1; /* [31] */
} pll_bit;
};
/**
* @brief crm misc1 register, offset:0x30
*/
union
{
__IO uint32_t misc1;
struct
{
__IO uint32_t hickcal_key : 8; /* [7:0] */
__IO uint32_t reserved1 : 8; /* [15:8] */
__IO uint32_t clkout_sel : 1; /* [16] */
__IO uint32_t reserved2 : 3; /* [19:17] */
__IO uint32_t clkflashsrc : 1; /* [20] */
__IO uint32_t reserved3 : 4; /* [24:21] */
__IO uint32_t hickdiv : 1; /* [25] */
__IO uint32_t reserved4 : 2; /* [27:26] */
__IO uint32_t clkoutdiv : 4; /* [31:28] */
} misc1_bit;
};
/**
* @brief crm reserved2 register, offset:0x50~0x34
*/
__IO uint32_t reserved2[8];
/**
* @brief crm misc2 register, offset:0x54
*/
union
{
__IO uint32_t misc2;
struct
{
__IO uint32_t reserved1 : 4; /* [3:0] */
__IO uint32_t auto_step_en : 2; /* [5:4] */
__IO uint32_t reserved2 : 3; /* [8:6] */
__IO uint32_t hick_to_sclk : 1; /* [9] */
__IO uint32_t reserved3 : 22;/* [31:10] */
} misc2_bit;
};
} crm_type;
/**
* @}
*/
#define CRM ((crm_type *) CRM_BASE)
/** @defgroup CRM_exported_functions
* @{
*/
void crm_reset(void);
void crm_lext_bypass(confirm_state new_state);
void crm_hext_bypass(confirm_state new_state);
flag_status crm_flag_get(uint32_t flag);
flag_status crm_interrupt_flag_get(uint32_t flag);
error_status crm_hext_stable_wait(void);
void crm_hick_clock_trimming_set(uint8_t trim_value);
void crm_hick_clock_calibration_set(uint8_t cali_value);
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state);
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
void crm_flag_clear(uint32_t flag);
void crm_ertc_clock_select(crm_ertc_clock_type value);
void crm_ertc_clock_enable(confirm_state new_state);
void crm_ahb_div_set(crm_ahb_div_type value);
void crm_apb1_div_set(crm_apb1_div_type value);
void crm_apb2_div_set(crm_apb2_div_type value);
void crm_adc_clock_div_set(crm_adc_div_type div_value);
void crm_clock_failure_detection_enable(confirm_state new_state);
void crm_battery_powered_domain_reset(confirm_state new_state);
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value);
void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type pll_fr);
void crm_sysclk_switch(crm_sclk_type value);
crm_sclk_type crm_sysclk_switch_status_get(void);
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
void crm_clock_out_set(crm_clkout_select_type clkout);
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
void crm_auto_step_mode_enable(confirm_state new_state);
void crm_hick_divider_select(crm_hick_div_6_type value);
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
void crm_clkout_div_set(crm_clkout_div_type clkout_div);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_debug.h
+156
View File
@@ -0,0 +1,156 @@
/**
**************************************************************************
* @file at32f421_debug.h
* @brief at32f421 debug header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_DEBUG_H
#define __AT32F421_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup DEBUG
* @{
*/
/** @defgroup DEBUG_mode_definition
* @{
*/
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
#define DEBUG_ERTC_PAUSE 0x00004000 /*!< debug ertc pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
#define DEBUG_TMR6_PAUSE 0x00080000 /*!< debug timer6 pause */
#define DEBUG_ERTC_512_PAUSE 0x00200000 /*!< debug ertc 512 pause */
#define DEBUG_TMR15_PAUSE 0x00400000 /*!< debug timer15 pause */
#define DEBUG_TMR16_PAUSE 0x00800000 /*!< debug timer16 pause */
#define DEBUG_TMR17_PAUSE 0x01000000 /*!< debug timer17 pause */
#define DEBUG_TMR14_PAUSE 0x08000000 /*!< debug timer14 pause */
/**
* @}
*/
/** @defgroup DEBUG_exported_types
* @{
*/
/**
* @brief type define debug register all
*/
typedef struct
{
/**
* @brief debug idcode register, offset:0x00
*/
union
{
__IO uint32_t pid;
struct
{
__IO uint32_t pid : 32;/* [31:0] */
} idcode_bit;
};
/**
* @brief debug ctrl register, offset:0x04
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t sleep_debug : 1;/* [0] */
__IO uint32_t deepsleep_debug : 1;/* [1] */
__IO uint32_t standby_debug : 1;/* [2] */
__IO uint32_t reserved1 : 5;/* [7:3] */
__IO uint32_t wdt_pause : 1;/* [8] */
__IO uint32_t wwdt_pause : 1;/* [9] */
__IO uint32_t tmr1_pause : 1;/* [10] */
__IO uint32_t reserved2 : 1;/* [11] */
__IO uint32_t tmr3_pause : 1;/* [12] */
__IO uint32_t reserved3 : 1;/* [13] */
__IO uint32_t ertc_pause : 1;/* [14] */
__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
__IO uint32_t reserved4 : 2;/* [18:17] */
__IO uint32_t tmr6_pause : 1;/* [19] */
__IO uint32_t reserved5 : 1;/* [20] */
__IO uint32_t ertc_512_pause : 1;/* [21] */
__IO uint32_t tmr15_pause : 1;/* [22] */
__IO uint32_t tmr16_pause : 1;/* [23] */
__IO uint32_t tmr17_pause : 1;/* [24] */
__IO uint32_t reserved6 : 2;/* [26:25] */
__IO uint32_t tmr14_pause : 1;/* [27] */
__IO uint32_t reserved7 : 4;/* [31:28] */
} ctrl_bit;
};
} debug_type;
/**
* @}
*/
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
/** @defgroup DEBUG_exported_functions
* @{
*/
uint16_t debug_device_id_get(void);
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_def.h
+69
View File
@@ -0,0 +1,69 @@
/**
**************************************************************************
* @file at32f421_def.h
* @brief at32f421 macros header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_DEF_H
#define __AT32F421_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* gnu compiler */
#if defined (__GNUC__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
#endif
#endif
/* arm compiler */
#if defined (__CC_ARM)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD __align(4)
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
/* iar compiler */
#if defined (__ICCARM__)
#ifndef ALIGNED_HEAD
#define ALIGNED_HEAD
#endif
#ifndef ALIGNED_TAIL
#define ALIGNED_TAIL
#endif
#endif
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_dma.h
+391
View File
@@ -0,0 +1,391 @@
/**
**************************************************************************
* @file at32f421_dma.h
* @brief at32f421 dma header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/**
at32f421 dma1 channel request(fixed) as folleow :
------------------------------------------------------------------------------------------------------
peripherals | channel1 | channel2 | channel3 | channel4 | channel5
------------------------------------------------------------------------------------------------------
adc | adc | | | |
------------------------------------------------------------------------------------------------------
spi/i2s | | spi1/i2s1_rx | spi1/i2s1_tx | spi2/i2s2_rx | spi2/i2s2_tx
------------------------------------------------------------------------------------------------------
usart1 | | usart1_tx | usart1_rx | usart1_tx | usart1_rx
------------------------------------------------------------------------------------------------------
usart2 | | | | usart2_tx | usart2_rx
------------------------------------------------------------------------------------------------------
i2c | | i2c1_tx | i2c1_rx | i2c2_tx | i2c2_rx
------------------------------------------------------------------------------------------------------
| | | | tmr1_ch4 | tmr1_ch3
tmr1 | | tmr1_ch1 | tmr1_ch2 | tmr1_trig | tmr1_overflow
| | | | tmr1_hall |
------------------------------------------------------------------------------------------------------
tmr3 | | tmr3_ch3 | tmr3_ch4 | tmr3_ch1 |
| | | tmr3_overflow | tmr3_trig |
------------------------------------------------------------------------------------------------------
tmr6 | | | tmr6_overflow | |
------------------------------------------------------------------------------------------------------
| | | | | tmr15_ch1
| | | | | tmr15_overflow
tmr15 | | | | | tmr15_trig
| | | | | tmr15_hall
| | | | | tmr15_ch2
------------------------------------------------------------------------------------------------------
tmr16 | | | tmr16_ch1 | tmr16_ch1 |
| | |tmr16_overflow |tmr16_overflow |
------------------------------------------------------------------------------------------------------
tmr17 | tmr17_ch1 | tmr17_ch1 | | |
|tmr17_overflow | tmr17_overflow | | |
------------------------------------------------------------------------------------------------------
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_DMA_H
#define __AT32F421_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_interrupts_definition
* @brief dma interrupt
* @{
*/
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @brief dma flag
* @{
*/
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
/**
* @}
*/
/** @defgroup DMA_exported_types
* @{
*/
/**
* @brief dma direction type
*/
typedef enum
{
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory
note:if the direction is memory to memory,peripheral_base_addr as source and memory_base_addr as destnation */
} dma_dir_type;
/**
* @brief dma peripheral incremented type
*/
typedef enum
{
DMA_PERIPHERAL_INC_DISABLE = 0x00, /*!< dma peripheral increment mode disable */
DMA_PERIPHERAL_INC_ENABLE = 0x01 /*!< dma peripheral increment mode enable */
} dma_peripheral_inc_type;
/**
* @brief dma memory incremented type
*/
typedef enum
{
DMA_MEMORY_INC_DISABLE = 0x00, /*!< dma memory increment mode disable */
DMA_MEMORY_INC_ENABLE = 0x01 /*!< dma memory increment mode enable */
} dma_memory_inc_type;
/**
* @brief dma peripheral data size type
*/
typedef enum
{
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
} dma_peripheral_data_size_type;
/**
* @brief dma memory data size type
*/
typedef enum
{
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
} dma_memory_data_size_type;
/**
* @brief dma priority level type
*/
typedef enum
{
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: mediue */
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
} dma_priority_level_type;
/**
* @brief dma init type
*/
typedef struct
{
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
uint32_t memory_base_addr; /*!< base addrress for memory */
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
uint16_t buffer_size; /*!< counter to transfer */
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
confirm_state loop_mode_enable; /*!< when circular mode enable, buffer size will reload if count to 0 */
dma_priority_level_type priority; /*!< dma priority can choose from very high, high, dedium or low */
} dma_init_type;
/**
* @brief type define dma register
*/
typedef struct
{
/**
* @brief dma sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t gf1 : 1; /* [0] */
__IO uint32_t fdtf1 : 1; /* [1] */
__IO uint32_t hdtf1 : 1; /* [2] */
__IO uint32_t dterrf1 : 1; /* [3] */
__IO uint32_t gf2 : 1; /* [4] */
__IO uint32_t fdtf2 : 1; /* [5] */
__IO uint32_t hdtf2 : 1; /* [6] */
__IO uint32_t dterrf2 : 1; /* [7] */
__IO uint32_t gf3 : 1; /* [8] */
__IO uint32_t fdtf3 : 1; /* [9] */
__IO uint32_t hdtf3 : 1; /* [10] */
__IO uint32_t dterrf3 : 1; /* [11] */
__IO uint32_t gf4 : 1; /* [12] */
__IO uint32_t fdtf4 : 1; /* [13] */
__IO uint32_t hdtf4 : 1; /* [14] */
__IO uint32_t dterrf4 : 1; /* [15] */
__IO uint32_t gf5 : 1; /* [16] */
__IO uint32_t fdtf5 : 1; /* [17] */
__IO uint32_t hdtf5 : 1; /* [18] */
__IO uint32_t dterrf5 : 1; /* [19] */
__IO uint32_t reserved1 : 12; /* [31:20] */
} sts_bit;
};
/**
* @brief dma clr register, offset:0x04
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t gfc1 : 1; /* [0] */
__IO uint32_t fdtfc1 : 1; /* [1] */
__IO uint32_t hdtfc1 : 1; /* [2] */
__IO uint32_t dterrfc1 : 1; /* [3] */
__IO uint32_t gfc2 : 1; /* [4] */
__IO uint32_t fdtfc2 : 1; /* [5] */
__IO uint32_t hdtfc2 : 1; /* [6] */
__IO uint32_t dterrfc2 : 1; /* [7] */
__IO uint32_t gfc3 : 1; /* [8] */
__IO uint32_t fdtfc3 : 1; /* [9] */
__IO uint32_t hdtfc3 : 1; /* [10] */
__IO uint32_t dterrfc3 : 1; /* [11] */
__IO uint32_t gfc4 : 1; /* [12] */
__IO uint32_t fdtfc4 : 1; /* [13] */
__IO uint32_t hdtfc4 : 1; /* [14] */
__IO uint32_t dterrfc4 : 1; /* [15] */
__IO uint32_t gfc5 : 1; /* [16] */
__IO uint32_t fdtfc5 : 1; /* [17] */
__IO uint32_t hdtfc5 : 1; /* [18] */
__IO uint32_t dterrfc5 : 1; /* [19] */
__IO uint32_t reserved1 : 12; /* [31:20] */
} clr_bit;
};
} dma_type;
/**
* @brief type define dma channel register all
*/
typedef struct
{
/**
* @brief dma ctrl register, offset:0x08+20*(x-1) x=1...5
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t chen : 1; /* [0] */
__IO uint32_t fdtien : 1; /* [1] */
__IO uint32_t hdtien : 1; /* [2] */
__IO uint32_t dterrien : 1; /* [3] */
__IO uint32_t dtd : 1; /* [4] */
__IO uint32_t lm : 1; /* [5] */
__IO uint32_t pincm : 1; /* [6] */
__IO uint32_t mincm : 1; /* [7] */
__IO uint32_t pwidth : 2; /* [9:8] */
__IO uint32_t mwidth : 2; /* [11:10] */
__IO uint32_t chpl : 2; /* [13:12] */
__IO uint32_t m2m : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} ctrl_bit;
};
/**
* @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...5
*/
union
{
__IO uint32_t dtcnt;
struct
{
__IO uint32_t cnt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dtcnt_bit;
};
/**
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...5
*/
union
{
__IO uint32_t paddr;
struct
{
__IO uint32_t paddr : 32;/* [31:0] */
} paddr_bit;
};
/**
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...5
*/
union
{
__IO uint32_t maddr;
struct
{
__IO uint32_t maddr : 32;/* [31:0] */
} maddr_bit;
};
} dma_channel_type;
/**
* @}
*/
#define DMA1 ((dma_type *) DMA1_BASE)
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
/** @defgroup DMA_exported_functions
* @{
*/
void dma_reset(dma_channel_type* dmax_channely);
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type* dma_init_struct);
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_ertc.h
+909
View File
@@ -0,0 +1,909 @@
/**
**************************************************************************
* @file at32f421_ertc.h
* @brief at32f421 ertc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_ERTC_H
#define __AT32F421_ERTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup ERTC
* @{
*/
/** @defgroup ERTC_interrupts_definition
* @brief ertc interrupt
* @{
*/
#define ERTC_TP_INT ((uint32_t)0x00000004) /*!< ertc tamper interrupt */
#define ERTC_ALA_INT ((uint32_t)0x00001000) /*!< ertc alarm a interrupt */
#define ERTC_TS_INT ((uint32_t)0x00008000) /*!< ertc timestamp interrupt */
/**
* @}
*/
/** @defgroup ERTC_flags_definition
* @brief ertc flag
* @{
*/
#define ERTC_ALAWF_FLAG ((uint32_t)0x00000001) /*!< ertc alarm a register allows write flag */
#define ERTC_TADJF_FLAG ((uint32_t)0x00000008) /*!< ertc time adjustment flag */
#define ERTC_INITF_FLAG ((uint32_t)0x00000010) /*!< ertc calendar initialization flag */
#define ERTC_UPDF_FLAG ((uint32_t)0x00000020) /*!< ertc calendar update flag */
#define ERTC_IMF_FLAG ((uint32_t)0x00000040) /*!< ertc enter initialization mode flag */
#define ERTC_ALAF_FLAG ((uint32_t)0x00000100) /*!< ertc alarm clock a flag */
#define ERTC_TSF_FLAG ((uint32_t)0x00000800) /*!< ertc timestamp flag */
#define ERTC_TSOF_FLAG ((uint32_t)0x00001000) /*!< ertc timestamp overflow flag */
#define ERTC_TP1F_FLAG ((uint32_t)0x00002000) /*!< ertc tamper detection 1 flag */
#define ERTC_CALUPDF_FLAG ((uint32_t)0x00010000) /*!< ertc calibration value update completed flag */
/**
* @brief ertc alarm mask
*/
#define ERTC_ALARM_MASK_NONE ((uint32_t)0x00000000) /*!< ertc alarm match all */
#define ERTC_ALARM_MASK_SEC ((uint32_t)0x00000080) /*!< ertc alarm don't match seconds */
#define ERTC_ALARM_MASK_MIN ((uint32_t)0x00008000) /*!< ertc alarm don't match minute */
#define ERTC_ALARM_MASK_HOUR ((uint32_t)0x00800000) /*!< ertc alarm don't match hour */
#define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */
#define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */
/**
* @}
*/
/** @defgroup ERTC_exported_types
* @{
*/
/**
* @brief ertc hour mode
*/
typedef enum
{
ERTC_HOUR_MODE_24 = 0x00, /*!< 24-hour format */
ERTC_HOUR_MODE_12 = 0x01 /*!< 12-hour format */
} ertc_hour_mode_set_type;
/**
* @brief ertc 12-hour format am/pm
*/
typedef enum
{
ERTC_24H = 0x00, /*!< 24-hour format */
ERTC_AM = 0x00, /*!< 12-hour format, ante meridiem */
ERTC_PM = 0x01 /*!< 12-hour format, meridiem */
} ertc_am_pm_type;
/**
* @brief ertc week or date select
*/
typedef enum
{
ERTC_SLECT_DATE = 0x00, /*!< slect date mode */
ERTC_SLECT_WEEK = 0x01 /*!< slect week mode */
} ertc_week_date_select_type;
/**
* @brief ertc alarm x select
*/
typedef enum
{
ERTC_ALA = 0x00, /*!< select alarm a */
} ertc_alarm_type;
/**
* @brief ertc alarm sub second mask
*/
typedef enum
{
ERTC_ALARM_SBS_MASK_ALL = 0x00, /*!< do not match the sub-second */
ERTC_ALARM_SBS_MASK_14_1 = 0x01, /*!< only compare bit [0] */
ERTC_ALARM_SBS_MASK_14_2 = 0x02, /*!< only compare bit [1:0] */
ERTC_ALARM_SBS_MASK_14_3 = 0x03, /*!< only compare bit [2:0] */
ERTC_ALARM_SBS_MASK_14_4 = 0x04, /*!< only compare bit [3:0] */
ERTC_ALARM_SBS_MASK_14_5 = 0x05, /*!< only compare bit [4:0] */
ERTC_ALARM_SBS_MASK_14_6 = 0x06, /*!< only compare bit [5:0] */
ERTC_ALARM_SBS_MASK_14_7 = 0x07, /*!< only compare bit [6:0] */
ERTC_ALARM_SBS_MASK_14_8 = 0x08, /*!< only compare bit [7:0] */
ERTC_ALARM_SBS_MASK_14_9 = 0x09, /*!< only compare bit [8:0] */
ERTC_ALARM_SBS_MASK_14_10 = 0x0A, /*!< only compare bit [9:0] */
ERTC_ALARM_SBS_MASK_14_11 = 0x0B, /*!< only compare bit [10:0] */
ERTC_ALARM_SBS_MASK_14_12 = 0x0C, /*!< only compare bit [11:0] */
ERTC_ALARM_SBS_MASK_14_13 = 0x0D, /*!< only compare bit [12:0] */
ERTC_ALARM_SBS_MASK_14 = 0x0E, /*!< only compare bit [13:0] */
ERTC_ALARM_SBS_MASK_NONE = 0x0F /*!< compare bit [14:0] */
} ertc_alarm_sbs_mask_type;
/**
* @brief ertc smooth calibration period
*/
typedef enum
{
ERTC_SMOOTH_CAL_PERIOD_32 = 0x00, /*!< 32 second calibration period */
ERTC_SMOOTH_CAL_PERIOD_16 = 0x01, /*!< 16 second calibration period */
ERTC_SMOOTH_CAL_PERIOD_8 = 0x02 /*!< 8 second calibration period */
} ertc_smooth_cal_period_type;
/**
* @brief ertc smooth calibration clock add mode
*/
typedef enum
{
ERTC_SMOOTH_CAL_CLK_ADD_0 = 0x00, /*!< do not increase clock */
ERTC_SMOOTH_CAL_CLK_ADD_512 = 0x01 /*!< add 512 clocks */
} ertc_smooth_cal_clk_add_type;
/**
* @brief ertc calibration output mode
*/
typedef enum
{
ERTC_CAL_OUTPUT_512HZ = 0x00, /*!< output 512 hz */
ERTC_CAL_OUTPUT_1HZ = 0x01 /*!< output 1 hz */
} ertc_cal_output_select_type;
/**
* @brief time adjust add mode
*/
typedef enum
{
ERTC_TIME_ADD_NONE = 0x00, /*!< none operation */
ERTC_TIME_ADD_1S = 0x01 /*!< add 1 second */
} ertc_time_adjust_type;
/**
* @brief ertc daylight saving time hour adjustment mode
*/
typedef enum
{
ERTC_DST_ADD_1H = 0x00, /*!< add 1 hour */
ERTC_DST_DEC_1H = 0x01 /*!< dec 1 hour */
} ertc_dst_operation_type;
/**
* @brief ertc daylight saving time store operation mode
*/
typedef enum
{
ERTC_DST_SAVE_0 = 0x00, /*!< set the bpr register value to 0 */
ERTC_DST_SAVE_1 = 0x01 /*!< set the bpr register value to 1 */
} ertc_dst_save_type;
/**
* @brief output source
*/
typedef enum
{
ERTC_OUTPUT_DISABLE = 0x00, /*!< diable output */
ERTC_OUTPUT_ALARM_A = 0x01, /*!< output alarm a event */
ERTC_OUTPUT_WAKEUP = 0x03 /*!< output wakeup event */
} ertc_output_source_type;
/**
* @brief output polarity
*/
typedef enum
{
ERTC_OUTPUT_POLARITY_HIGH = 0x00, /*!< when the event occurs, the output is high */
ERTC_OUTPUT_POLARITY_LOW = 0x01 /*!< when the event occurs, the output is low */
} ertc_output_polarity_type;
/**
* @brief output type
*/
typedef enum
{
ERTC_OUTPUT_TYPE_OPEN_DRAIN = 0x00, /*!< open drain output */
ERTC_OUTPUT_TYPE_PUSH_PULL = 0x01 /*!< push pull output */
} ertc_output_type;
/**
* @brief ertc timestamp valid edge
*/
typedef enum
{
ERTC_TIMESTAMP_EDGE_RISING = 0x00, /*!< rising edge trigger */
ERTC_TIMESTAMP_EDGE_FALLING = 0x01 /*!< falling edge trigger */
} ertc_timestamp_valid_edge_type;
/**
* @brief ertc tamper x select
*/
typedef enum
{
ERTC_TAMPER_1 = 0x00, /*!< tamper 1 */
} ertc_tamper_select_type;
/**
* @brief tamper detection pre-charge time
*/
typedef enum
{
ERTC_TAMPER_PR_1_ERTCCLK = 0x00, /*!< pre-charge time is 1 ERTC_CLK */
ERTC_TAMPER_PR_2_ERTCCLK = 0x01, /*!< pre-charge time is 2 ERTC_CLK */
ERTC_TAMPER_PR_4_ERTCCLK = 0x02, /*!< pre-charge time is 4 ERTC_CLK */
ERTC_TAMPER_PR_8_ERTCCLK = 0x03 /*!< pre-charge time is 8 ERTC_CLK */
} ertc_tamper_precharge_type;
/**
* @brief ertc tamper filter
*/
typedef enum
{
ERTC_TAMPER_FILTER_DISABLE = 0x00, /*!< disable filter function */
ERTC_TAMPER_FILTER_2 = 0x01, /*!< 2 consecutive samples arw valid, effective tamper event */
ERTC_TAMPER_FILTER_4 = 0x02, /*!< 4 consecutive samples arw valid, effective tamper event */
ERTC_TAMPER_FILTER_8 = 0x03 /*!< 8 consecutive samples arw valid, effective tamper event */
} ertc_tamper_filter_type;
/**
* @brief ertc tamper detection frequency
*/
typedef enum
{
ERTC_TAMPER_FREQ_DIV_32768 = 0x00, /*!< ERTC_CLK / 32768 */
ERTC_TAMPER_FREQ_DIV_16384 = 0x01, /*!< ERTC_CLK / 16384 */
ERTC_TAMPER_FREQ_DIV_8192 = 0x02, /*!< ERTC_CLK / 8192 */
ERTC_TAMPER_FREQ_DIV_4096 = 0x03, /*!< ERTC_CLK / 4096 */
ERTC_TAMPER_FREQ_DIV_2048 = 0x04, /*!< ERTC_CLK / 2048 */
ERTC_TAMPER_FREQ_DIV_1024 = 0x05, /*!< ERTC_CLK / 1024 */
ERTC_TAMPER_FREQ_DIV_512 = 0x06, /*!< ERTC_CLK / 512 */
ERTC_TAMPER_FREQ_DIV_256 = 0x07 /*!< ERTC_CLK / 256 */
} ertc_tamper_detect_freq_type;
/**
* @brief ertc tamper valid edge
*/
typedef enum
{
ERTC_TAMPER_EDGE_RISING = 0x00, /*!< rising gedge */
ERTC_TAMPER_EDGE_FALLING = 0x01, /*!< falling gedge */
ERTC_TAMPER_EDGE_LOW = 0x00, /*!< low level */
ERTC_TAMPER_EDGE_HIGH = 0x01 /*!< high level */
} ertc_tamper_valid_edge_type;
/**
* @brief ertc bpr register
*/
typedef enum
{
ERTC_DT1 = 0, /*!< bpr data register 0 */
ERTC_DT2 = 1, /*!< bpr data register 1 */
ERTC_DT3 = 2, /*!< bpr data register 2 */
ERTC_DT4 = 3, /*!< bpr data register 3 */
ERTC_DT5 = 4, /*!< bpr data register 4 */
} ertc_dt_type;
/**
* @brief ertc time
*/
typedef struct
{
uint8_t year; /*!< year */
uint8_t month; /*!< month */
uint8_t day; /*!< date */
uint8_t hour; /*!< hour */
uint8_t min; /*!< minute */
uint8_t sec; /*!< second */
uint8_t week; /*!< week */
ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
} ertc_time_type;
/**
* @brief ertc alarm
*/
typedef struct
{
uint8_t day; /*!< date */
uint8_t hour; /*!< hour */
uint8_t min; /*!< minute */
uint8_t sec; /*!< second */
ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
uint32_t mask; /*!< alarm mask*/
uint8_t week_date_sel; /*!< week or date mode */
uint8_t week; /*!< week */
} ertc_alarm_value_type;
/**
* @brief ertc time reg union
*/
typedef union
{
__IO uint32_t time;
struct
{
__IO uint32_t s : 7; /* [6:0] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t m : 7; /* [14:8] */
__IO uint32_t reserved2 : 1; /* [15] */
__IO uint32_t h : 6; /* [21:16] */
__IO uint32_t ampm : 1; /* [22] */
__IO uint32_t reserved3 : 9; /* [31:23] */
} time_bit;
} ertc_reg_time_type;
/**
* @brief ertc date reg union
*/
typedef union
{
__IO uint32_t date;
struct
{
__IO uint32_t d :6; /* [5:0] */
__IO uint32_t reserved1 :2; /* [7:6] */
__IO uint32_t m :5; /* [12:8] */
__IO uint32_t wk :3; /* [15:13] */
__IO uint32_t y :8; /* [23:16] */
__IO uint32_t reserved2 :8; /* [31:24] */
} date_bit;
} ertc_reg_date_type;
/**
* @brief ertc alarm reg union
*/
typedef union
{
__IO uint32_t ala;
struct
{
__IO uint32_t s :7; /* [6:0] */
__IO uint32_t mask1 :1; /* [7] */
__IO uint32_t m :7; /* [14:8] */
__IO uint32_t mask2 :1; /* [15] */
__IO uint32_t h :6; /* [21:16] */
__IO uint32_t ampm :1; /* [22] */
__IO uint32_t mask3 :1; /* [23] */
__IO uint32_t d :6; /* [29:24] */
__IO uint32_t wksel :1; /* [30] */
__IO uint32_t mask4 :1; /* [31] */
} ala_bit;
} ertc_reg_alarm_type;
/**
* @brief ertc scal reg union
*/
typedef union
{
__IO uint32_t scal;
struct
{
__IO uint32_t dec :9; /* [8:0] */
__IO uint32_t reserved1 :4; /* [12:9] */
__IO uint32_t cal16 :1; /* [13] */
__IO uint32_t cal8 :1; /* [14] */
__IO uint32_t add :1; /* [15] */
__IO uint32_t reserved2 :16;/* [31:16] */
} scal_bit;
} ertc_reg_scal_type;
/**
* @brief ertc tadj reg union
*/
typedef union
{
__IO uint32_t tadj;
struct
{
__IO uint32_t decsbs :15;/* [14:0] */
__IO uint32_t reserved1 :16;/* [30:15] */
__IO uint32_t add1s :1; /* [31] */
} tadj_bit;
} ertc_reg_tadj_type;
/**
* @brief ertc tstm reg union
*/
typedef union
{
__IO uint32_t tstm;
struct
{
__IO uint32_t s :7; /* [6:0] */
__IO uint32_t reserved1 :1; /* [7] */
__IO uint32_t m :7; /* [14:8] */
__IO uint32_t reserved2 :1; /* [15] */
__IO uint32_t h :6; /* [21:16] */
__IO uint32_t ampm :1; /* [22] */
__IO uint32_t reserved3 :9; /* [31:23] */
} tstm_bit;
} ertc_reg_tstm_type;
/**
* @brief ertc tsdt register, offset:0x34
*/
typedef union
{
__IO uint32_t tsdt;
struct
{
__IO uint32_t d :6; /* [5:0] */
__IO uint32_t reserved1 :2; /* [7:6] */
__IO uint32_t m :5; /* [12:8] */
__IO uint32_t wk :3; /* [15:13] */
__IO uint32_t reserved2 :16;/* [31:16] */
} tsdt_bit;
} ertc_reg_tsdt_type;
/**
* @brief type define ertc register all
*/
typedef struct
{
/**
* @brief ertc time register, offset:0x00
*/
union
{
__IO uint32_t time;
struct
{
__IO uint32_t s : 7; /* [6:0] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t m : 7; /* [14:8] */
__IO uint32_t reserved2 : 1; /* [15] */
__IO uint32_t h : 6; /* [21:16] */
__IO uint32_t ampm : 1; /* [22] */
__IO uint32_t reserved3 : 9; /* [31:23] */
} time_bit;
};
/**
* @brief ertc date register, offset:0x04
*/
union
{
__IO uint32_t date;
struct
{
__IO uint32_t d :6; /* [5:0] */
__IO uint32_t reserved1 :2; /* [7:6] */
__IO uint32_t m :5; /* [12:8] */
__IO uint32_t wk :3; /* [15:13] */
__IO uint32_t y :8; /* [23:16] */
__IO uint32_t reserved2 :8; /* [31:24] */
} date_bit;
};
/**
* @brief ertc ctrl register, offset:0x08
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t reserved1 :3; /* [2:0] */
__IO uint32_t tsedg :1; /* [3] */
__IO uint32_t rcden :1; /* [4] */
__IO uint32_t dren :1; /* [5] */
__IO uint32_t hm :1; /* [6] */
__IO uint32_t reserved2 :1; /* [7] */
__IO uint32_t alaen :1; /* [8] */
__IO uint32_t reserved3 :1; /* [9] */
__IO uint32_t reserved4 :1; /* [10] */
__IO uint32_t tsen :1; /* [11] */
__IO uint32_t alaien :1; /* [12] */
__IO uint32_t reserved5 :1; /* [13] */
__IO uint32_t reserved6 :1; /* [14] */
__IO uint32_t tsien :1; /* [15] */
__IO uint32_t add1h :1; /* [16] */
__IO uint32_t dec1h :1; /* [17] */
__IO uint32_t bpr :1; /* [18] */
__IO uint32_t calosel :1; /* [19] */
__IO uint32_t outp :1; /* [20] */
__IO uint32_t outsel :2; /* [22:21] */
__IO uint32_t caloen :1; /* [23] */
__IO uint32_t reserved7 :8; /* [31:24] */
} ctrl_bit;
};
/**
* @brief ertc sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t alawf :1; /* [0] */
__IO uint32_t reserved1 :1; /* [1] */
__IO uint32_t reserved2 :1; /* [2] */
__IO uint32_t tadjf :1; /* [3] */
__IO uint32_t initf :1; /* [4] */
__IO uint32_t updf :1; /* [5] */
__IO uint32_t imf :1; /* [6] */
__IO uint32_t imen :1; /* [7] */
__IO uint32_t alaf :1; /* [8] */
__IO uint32_t reserved3 :1; /* [9] */
__IO uint32_t reserved4 :1; /* [10] */
__IO uint32_t tsf :1; /* [11] */
__IO uint32_t tsof :1; /* [12] */
__IO uint32_t tp1f :1; /* [13] */
__IO uint32_t reserved5 :1; /* [14] */
__IO uint32_t reserved6 :1; /* [15] */
__IO uint32_t calupdf :1; /* [16] */
__IO uint32_t reserved7 :15;/* [31:17] */
} sts_bit;
};
/**
* @brief ertc div register, offset:0x10
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t divb :15;/* [14:0] */
__IO uint32_t reserved1 :1; /* [15] */
__IO uint32_t diva :7; /* [22:16] */
__IO uint32_t reserved2 :9; /* [31:23] */
} div_bit;
};
/**
* @brief ertc reserved register, offset:0x14
*/
__IO uint32_t reserved1;
/**
* @brief ertc reserved register, offset:0x18
*/
__IO uint32_t reserved2;
/**
* @brief ertc ala register, offset:0x1C
*/
union
{
__IO uint32_t ala;
struct
{
__IO uint32_t s :7; /* [6:0] */
__IO uint32_t mask1 :1; /* [7] */
__IO uint32_t m :7; /* [14:8] */
__IO uint32_t mask2 :1; /* [15] */
__IO uint32_t h :6; /* [21:16] */
__IO uint32_t ampm :1; /* [22] */
__IO uint32_t mask3 :1; /* [23] */
__IO uint32_t d :6; /* [29:24] */
__IO uint32_t wksel :1; /* [30] */
__IO uint32_t mask4 :1; /* [31] */
} ala_bit;
};
/**
* @brief ertc reserved register, offset:0x20
*/
__IO uint32_t reserved3;
/**
* @brief ertc wp register, offset:0x24
*/
union
{
__IO uint32_t wp;
struct
{
__IO uint32_t cmd :8; /* [7:0] */
__IO uint32_t reserved1 :24;/* [31:8] */
} wp_bit;
};
/**
* @brief ertc sbs register, offset:0x28
*/
union
{
__IO uint32_t sbs;
struct
{
__IO uint32_t sbs :16;/* [15:0] */
__IO uint32_t reserved1 :16;/* [31:16] */
} sbs_bit;
};
/**
* @brief ertc tadj register, offset:0x2C
*/
union
{
__IO uint32_t tadj;
struct
{
__IO uint32_t decsbs :15;/* [14:0] */
__IO uint32_t reserved1 :16;/* [30:15] */
__IO uint32_t add1s :1; /* [31] */
} tadj_bit;
};
/**
* @brief ertc tstm register, offset:0x30
*/
union
{
__IO uint32_t tstm;
struct
{
__IO uint32_t s :7; /* [6:0] */
__IO uint32_t reserved1 :1; /* [7] */
__IO uint32_t m :7; /* [14:8] */
__IO uint32_t reserved2 :1; /* [15] */
__IO uint32_t h :6; /* [21:16] */
__IO uint32_t ampm :1; /* [22] */
__IO uint32_t reserved3 :9; /* [31:23] */
} tstm_bit;
};
/**
* @brief ertc tsdt register, offset:0x34
*/
union
{
__IO uint32_t tsdt;
struct
{
__IO uint32_t d :6; /* [5:0] */
__IO uint32_t reserved1 :2; /* [7:6] */
__IO uint32_t m :5; /* [12:8] */
__IO uint32_t wk :3; /* [15:13] */
__IO uint32_t reserved2 :16;/* [31:16] */
} tsdt_bit;
};
/**
* @brief ertc tssbs register, offset:0x38
*/
union
{
__IO uint32_t tssbs;
struct
{
__IO uint32_t sbs :16;/* [15:0] */
__IO uint32_t reserved1 :16;/* [31:16] */
} tssbs_bit;
};
/**
* @brief ertc scal register, offset:0x3C
*/
union
{
__IO uint32_t scal;
struct
{
__IO uint32_t dec :9; /* [8:0] */
__IO uint32_t reserved1 :4; /* [12:9] */
__IO uint32_t cal16 :1; /* [13] */
__IO uint32_t cal8 :1; /* [14] */
__IO uint32_t add :1; /* [15] */
__IO uint32_t reserved2 :16;/* [31:16] */
} scal_bit;
};
/**
* @brief ertc tamp register, offset:0x40
*/
union
{
__IO uint32_t tamp;
struct
{
__IO uint32_t tp1en :1; /* [0] */
__IO uint32_t tp1edg :1; /* [1] */
__IO uint32_t tpien :1; /* [2] */
__IO uint32_t reserved1 :1; /* [3] */
__IO uint32_t reserved2 :1; /* [4] */
__IO uint32_t reserved3 :2; /* [6:5] */
__IO uint32_t tptsen :1; /* [7] */
__IO uint32_t tpfreq :3; /* [10:8] */
__IO uint32_t tpflt :2; /* [12:11] */
__IO uint32_t tppr :2; /* [14:13] */
__IO uint32_t tppu :1; /* [15] */
__IO uint32_t reserved4 :1; /* [16] */
__IO uint32_t reserved5 :1; /* [17] */
__IO uint32_t outtype :1; /* [18] */
__IO uint32_t reserved6 :13;/* [31:19] */
} tamp_bit;
};
/**
* @brief ertc alasbs register, offset:0x44
*/
union
{
__IO uint32_t alasbs;
struct
{
__IO uint32_t sbs :15;/* [14:0] */
__IO uint32_t reserved1 :9; /* [23:15] */
__IO uint32_t sbsmsk :4; /* [27:24] */
__IO uint32_t reserved2 :4; /* [31:28] */
} alasbs_bit;
};
/**
* @brief ertc reserved register, offset:0x48
*/
__IO uint32_t reserved4;
/**
* @brief reserved register, offset:0x4c
*/
__IO uint32_t reserved5;
/**
* @brief ertc dt1 register, offset:0x50
*/
union
{
__IO uint32_t dt1;
struct
{
__IO uint32_t dt :32;/* [31:0] */
} dt1_bit;
};
/**
* @brief ertc dt2 register, offset:0x54
*/
union
{
__IO uint32_t dt2;
struct
{
__IO uint32_t dt :32;/* [31:0] */
} dt2_bit;
};
/**
* @brief ertc dt3 register, offset:0x58
*/
union
{
__IO uint32_t dt3;
struct
{
__IO uint32_t dt :32;/* [31:0] */
} dt3_bit;
};
/**
* @brief ertc dt4 register, offset:0x5C
*/
union
{
__IO uint32_t dt4;
struct
{
__IO uint32_t dt :32;/* [31:0] */
} dt4_bit;
};
/**
* @brief ertc dt5 register, offset:0x60
*/
union
{
__IO uint32_t dt5;
struct
{
__IO uint32_t dt :32;/* [31:0] */
} dt5_bit;
};
} ertc_type;
/**
* @}
*/
#define ERTC ((ertc_type *) ERTC_BASE)
/** @defgroup ERTC_exported_functions
* @{
*/
uint8_t ertc_num_to_bcd(uint8_t num);
uint8_t ertc_bcd_to_num(uint8_t bcd);
void ertc_write_protect_enable(void);
void ertc_write_protect_disable(void);
error_status ertc_wait_update(void);
error_status ertc_wait_flag(uint32_t flag, flag_status status);
error_status ertc_init_mode_enter(void);
void ertc_init_mode_exit(void);
error_status ertc_reset(void);
error_status ertc_divider_set(uint16_t div_a, uint16_t div_b);
error_status ertc_hour_mode_set(ertc_hour_mode_set_type mode);
error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week);
error_status ertc_time_set(uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
void ertc_calendar_get(ertc_time_type* time);
uint32_t ertc_sub_second_get(void);
void ertc_alarm_mask_set(ertc_alarm_type alarm_x, uint32_t mask);
void ertc_alarm_week_date_select(ertc_alarm_type alarm_x, ertc_week_date_select_type wk);
void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
void ertc_alarm_sub_second_set(ertc_alarm_type alarm_x, uint32_t value, ertc_alarm_sbs_mask_type mask);
error_status ertc_alarm_enable(ertc_alarm_type alarm_x, confirm_state new_state);
void ertc_alarm_get(ertc_alarm_type alarm_x, ertc_alarm_value_type* alarm);
uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x);
error_status ertc_smooth_calibration_config(ertc_smooth_cal_period_type period, ertc_smooth_cal_clk_add_type clk_add, uint32_t clk_dec);
void ertc_cal_output_select(ertc_cal_output_select_type output);
void ertc_cal_output_enable(confirm_state new_state);
error_status ertc_time_adjust(ertc_time_adjust_type add1s, uint32_t decsbs);
void ertc_daylight_set(ertc_dst_operation_type operation, ertc_dst_save_type save);
uint8_t ertc_daylight_bpr_get(void);
error_status ertc_refer_clock_detect_enable(confirm_state new_state);
void ertc_direct_read_enable(confirm_state new_state);
void ertc_output_set(ertc_output_source_type source, ertc_output_polarity_type polarity, ertc_output_type type);
void ertc_timestamp_valid_edge_set(ertc_timestamp_valid_edge_type edge);
void ertc_timestamp_enable(confirm_state new_state);
void ertc_timestamp_get(ertc_time_type* time);
uint32_t ertc_timestamp_sub_second_get(void);
void ertc_tamper_pull_up_enable(confirm_state new_state);
void ertc_tamper_precharge_set(ertc_tamper_precharge_type precharge);
void ertc_tamper_filter_set(ertc_tamper_filter_type filter);
void ertc_tamper_detect_freq_set(ertc_tamper_detect_freq_type freq);
void ertc_tamper_valid_edge_set(ertc_tamper_select_type tamper_x, ertc_tamper_valid_edge_type trigger);
void ertc_tamper_timestamp_enable(confirm_state new_state);
void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_state);
void ertc_interrupt_enable(uint32_t source, confirm_state new_state);
flag_status ertc_interrupt_get(uint32_t source);
flag_status ertc_flag_get(uint32_t flag);
flag_status ertc_interrupt_flag_get(uint32_t flag);
void ertc_flag_clear(uint32_t flag);
void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data);
uint32_t ertc_bpr_data_read(ertc_dt_type dt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_exint.h
+231
View File
@@ -0,0 +1,231 @@
/**
**************************************************************************
* @file at32f421_exint.h
* @brief at32f421 exint header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_EXINT_H
#define __AT32F421_EXINT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup EXINT
* @{
*/
/** @defgroup EXINT_lines
* @{
*/
#define EXINT_LINE_NONE ((uint32_t)0x000000)
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the ertc alarm event */
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 connected to the cmp wakeup from suspend event */
/**
* @}
*/
/** @defgroup EXINT_exported_types
* @{
*/
/**
* @brief exint line mode type
*/
typedef enum
{
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
EXINT_LINE_INTERRUPT = 0x00, /*!< same as EXINT_LINE_INTERRUPUT, fixed spelling error */
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
} exint_line_mode_type;
/**
* @brief exint polarity configuration type
*/
typedef enum
{
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
} exint_polarity_config_type;
/**
* @brief exint init type
*/
typedef struct
{
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
confirm_state line_enable; /*!< enable or disable exint */
} exint_init_type;
/**
* @brief type define exint register all
*/
typedef struct
{
/**
* @brief exint inten register, offset:0x00
*/
union
{
__IO uint32_t inten;
struct
{
__IO uint32_t intenx : 22;/* [21:0] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} inten_bit;
};
/**
* @brief exint evten register, offset:0x04
*/
union
{
__IO uint32_t evten;
struct
{
__IO uint32_t evtenx : 22;/* [21:0] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} evten_bit;
};
/**
* @brief exint polcfg1 register, offset:0x08
*/
union
{
__IO uint32_t polcfg1;
struct
{
__IO uint32_t rpx : 22;/* [21:0] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} polcfg1_bit;
};
/**
* @brief exint polcfg2 register, offset:0x0C
*/
union
{
__IO uint32_t polcfg2;
struct
{
__IO uint32_t fpx : 22;/* [21:0] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} polcfg2_bit;
};
/**
* @brief exint swtrg register, offset:0x10
*/
union
{
__IO uint32_t swtrg;
struct
{
__IO uint32_t swtx : 22;/* [21:0] */
__IO uint32_t reserved1 : 10;/* [31:22] */
} swtrg_bit;
};
/**
* @brief exint intsts register, offset:0x14
*/
union
{
__IO uint32_t intsts;
struct
{
__IO uint32_t linex : 20;/* [21:0] */
__IO uint32_t reserved1 : 12;/* [31:22] */
} intsts_bit;
};
} exint_type;
/**
* @}
*/
#define EXINT ((exint_type *) EXINT_BASE)
/** @defgroup EXINT_exported_functions
* @{
*/
void exint_reset(void);
void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
flag_status exint_interrupt_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_flash.h
+570
View File
@@ -0,0 +1,570 @@
/**
**************************************************************************
* @file at32f421_flash.h
* @brief at32f421 flash header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_FLASH_H
#define __AT32F421_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_keys
* @brief flash keys
* @{
*/
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
#define FAP_HIGH_LEVEL_KEY ((uint16_t)0x00CC) /*!< flash fap high level enable key val */
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
/**
* @}
*/
/** @defgroup FLASH_flags
* @brief flash flag
* @{
*/
#define FLASH_OBF_FLAG ((uint32_t)0x00000001) /*!< flash operate busy flag */
#define FLASH_ODF_FLAG ((uint32_t)0x00000020) /*!< flash operate done flag */
#define FLASH_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash program error flag */
#define FLASH_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash erase/program protection error flag */
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
/**
* @}
*/
/** @defgroup FLASH_interrupts
* @brief flash interrupts
* @{
*/
#define FLASH_ERR_INT ((uint32_t)0x00000001) /*!< flash error interrupt */
#define FLASH_ODF_INT ((uint32_t)0x00000002) /*!< flash operate done interrupt */
/**
* @}
*/
/** @defgroup FLASH_slib_mask
* @brief flash slib mask
* @{
*/
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x000007FF) /*!< flash slib start sector */
#define FLASH_SLIB_INST_START_SECTOR ((uint32_t)0x003FF800) /*!< flash slib i-bus area start sector */
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFC00000) /*!< flash slib end sector */
/**
* @}
*/
/** @defgroup FLASH_user_system_data
* @brief flash user system data
* @{
*/
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
#define USD_BOOT1_LOW ((uint16_t)0x0010) /*!< when boot0 is high level, boot from bootmem */
#define USD_BOOT1_HIGH ((uint16_t)0x0000) /*!< when boot0 is high level, boot from sram */
/**
* @}
*/
/** @defgroup FLASH_timeout_definition
* @brief flash timeout definition
* @{
*/
#define ERASE_TIMEOUT ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
/**
* @}
*/
/**
* @brief set the flash psr register
* @param wtcyc: the flash wait cycle.
* this parameter can be one of the following values:
* - FLASH_WAIT_CYCLE_0
* - FLASH_WAIT_CYCLE_1
* - FLASH_WAIT_CYCLE_2
* - FLASH_WAIT_CYCLE_3
*/
#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x150 | wtcyc))
/** @defgroup FLASH_exported_types
* @{
*/
/**
* @brief flash status type
*/
typedef enum
{
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
} flash_status_type;
/**
* @brief flash wait cycle type
*/
typedef enum
{
FLASH_WAIT_CYCLE_0 = 0x00, /*!< sysclk 1~32mhz */
FLASH_WAIT_CYCLE_1 = 0x01, /*!< sysclk 33~64mhz */
FLASH_WAIT_CYCLE_2 = 0x02, /*!< sysclk 65~96mhz */
FLASH_WAIT_CYCLE_3 = 0x03 /*!< sysclk 97~120mhz */
} flash_wait_cycle_type;
/**
* @brief type define flash register all
*/
typedef struct
{
/**
* @brief flash psr register, offset:0x00
*/
union
{
__IO uint32_t psr;
struct
{
__IO uint32_t wtcyc : 3; /* [2:0] */
__IO uint32_t hfcyc_en : 1; /* [3] */
__IO uint32_t pft_en : 1; /* [4] */
__IO uint32_t pft_enf : 1; /* [5] */
__IO uint32_t pft_en2 : 1; /* [6] */
__IO uint32_t pft_enf2 : 1; /* [7] */
__IO uint32_t pft_lat_dis : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} psr_bit;
};
/**
* @brief flash unlock register, offset:0x04
*/
union
{
__IO uint32_t unlock;
struct
{
__IO uint32_t ukval : 32;/* [31:0] */
} unlock_bit;
};
/**
* @brief flash usd unlock register, offset:0x08
*/
union
{
__IO uint32_t usd_unlock;
struct
{
__IO uint32_t usd_ukval : 32;/* [31:0] */
} usd_unlock_bit;
};
/**
* @brief flash sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t obf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t prgmerr : 1; /* [2] */
__IO uint32_t reserved2 : 1; /* [3] */
__IO uint32_t epperr : 1; /* [4] */
__IO uint32_t odf : 1; /* [5] */
__IO uint32_t reserved3 : 26;/* [31:6] */
} sts_bit;
};
/**
* @brief flash ctrl register, offset:0x10
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t fprgm : 1; /* [0] */
__IO uint32_t secers : 1; /* [1] */
__IO uint32_t bankers : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t usdprgm : 1; /* [4] */
__IO uint32_t usders : 1; /* [5] */
__IO uint32_t erstr : 1; /* [6] */
__IO uint32_t oplk : 1; /* [7] */
__IO uint32_t reserved2 : 1; /* [8] */
__IO uint32_t usdulks : 1; /* [9] */
__IO uint32_t errie : 1; /* [10] */
__IO uint32_t reserved3 : 1; /* [11] */
__IO uint32_t odfie : 1; /* [12] */
__IO uint32_t reserved4 : 3; /* [15:13] */
__IO uint32_t fap_hl_dis : 1; /* [16] */
__IO uint32_t lpmen : 1; /* [17] */
__IO uint32_t reserved5 : 14;/* [31:18] */
} ctrl_bit;
};
/**
* @brief flash addr register, offset:0x14
*/
union
{
__IO uint32_t addr;
struct
{
__IO uint32_t fa : 32;/* [31:0] */
} addr_bit;
};
/**
* @brief flash reserved1 register, offset:0x18
*/
__IO uint32_t reserved1;
/**
* @brief flash usd register, offset:0x1C
*/
union
{
__IO uint32_t usd;
struct
{
__IO uint32_t usderr : 1; /* [0] */
__IO uint32_t fap : 1; /* [1] */
__IO uint32_t wdt_ato_en : 1; /* [2] */
__IO uint32_t depslp_rst : 1; /* [3] */
__IO uint32_t stdby_rst : 1; /* [4] */
__IO uint32_t reserved1 : 1; /* [5] */
__IO uint32_t boot1 : 1; /* [6] */
__IO uint32_t reserved2 : 3; /* [9:7] */
__IO uint32_t user_d0 : 8; /* [17:10] */
__IO uint32_t user_d1 : 8; /* [25:18] */
__IO uint32_t fap_hl : 1; /* [26] */
__IO uint32_t reserved3 : 5; /* [31:27] */
} usd_bit;
};
/**
* @brief flash epps register, offset:0x20
*/
union
{
__IO uint32_t epps;
struct
{
__IO uint32_t epps : 32;/* [31:0] */
} epps_bit;
};
/**
* @brief flash reserved2 register, offset:0x70~0x24
*/
__IO uint32_t reserved2[20];
/**
* @brief flash slib_sts0 register, offset:0x74
*/
union
{
__IO uint32_t slib_sts0;
struct
{
__IO uint32_t btm_ap_enf : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t em_slib_enf : 1; /* [2] */
__IO uint32_t slib_enf : 1; /* [3] */
__IO uint32_t reserved2 : 12;/* [15:4] */
__IO uint32_t em_slib_inst_ss : 8; /* [23:16] */
__IO uint32_t reserved3 : 8; /* [31:24] */
} slib_sts0_bit;
};
/**
* @brief flash slib_sts1 register, offset:0x78
*/
union
{
__IO uint32_t slib_sts1;
struct
{
__IO uint32_t slib_ss : 11;/* [10:0] */
__IO uint32_t slib_inst_ss : 11;/* [21:11] */
__IO uint32_t slib_es : 10;/* [31:22] */
} slib_sts1_bit;
};
/**
* @brief flash slib_pwd_clr register, offset:0x7C
*/
union
{
__IO uint32_t slib_pwd_clr;
struct
{
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
} slib_pwd_clr_bit;
};
/**
* @brief flash slib_misc_sts register, offset:0x80
*/
union
{
__IO uint32_t slib_misc_sts;
struct
{
__IO uint32_t slib_pwd_err : 1; /* [0] */
__IO uint32_t slib_pwd_ok : 1; /* [1] */
__IO uint32_t slib_ulkf : 1; /* [2] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} slib_misc_sts_bit;
};
/**
* @brief flash crc_addr register, offset:0x84
*/
union
{
__IO uint32_t crc_addr;
struct
{
__IO uint32_t crc_addr : 32;/* [31:0] */
} crc_addr_bit;
};
/**
* @brief flash crc_ctrl register, offset:0x88
*/
union
{
__IO uint32_t crc_ctrl;
struct
{
__IO uint32_t crc_sn : 16;/* [15:0] */
__IO uint32_t crc_strt : 1; /* [16] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} crc_ctrl_bit;
};
/**
* @brief flash crc_chkr register, offset:0x8C
*/
union
{
__IO uint32_t crc_chkr;
struct
{
__IO uint32_t crc_chkr : 32;/* [31:0] */
} crc_chkr_bit;
};
/**
* @brief flash reserved3 register, offset:0x15C~0x90
*/
__IO uint32_t reserved3[52];
/**
* @brief flash slib_set_pwd register, offset:0x160
*/
union
{
__IO uint32_t slib_set_pwd;
struct
{
__IO uint32_t slib_pset_val : 32;/* [31:0] */
} slib_set_pwd_bit;
};
/**
* @brief flash slib_set_range register, offset:0x164
*/
union
{
__IO uint32_t slib_set_range;
struct
{
__IO uint32_t slib_ss_set : 11;/* [10:0] */
__IO uint32_t slib_iss_set : 11;/* [21:11] */
__IO uint32_t slib_es_set : 10;/* [31:22] */
} slib_set_range_bit;
};
/**
* @brief flash em_slib_set register, offset:0x168
*/
union
{
__IO uint32_t em_slib_set;
struct
{
__IO uint32_t em_slib_set : 16;/* [15:0] */
__IO uint32_t em_slib_iss_set : 8; /* [23:16] */
__IO uint32_t reserved1 : 8; /* [31:24] */
} em_slib_set_bit;
};
/**
* @brief flash btm_mode_set register, offset:0x16C
*/
union
{
__IO uint32_t btm_mode_set;
struct
{
__IO uint32_t btm_mode_set : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} btm_mode_set_bit;
};
/**
* @brief flash slib_unlock register, offset:0x170
*/
union
{
__IO uint32_t slib_unlock;
struct
{
__IO uint32_t slib_ukval : 32;/* [31:0] */
} slib_unlock_bit;
};
} flash_type;
/**
* @brief user system data
*/
typedef struct
{
__IO uint16_t fap;
__IO uint16_t ssb;
__IO uint16_t data0;
__IO uint16_t data1;
__IO uint16_t epp0;
__IO uint16_t epp1;
__IO uint16_t epp2;
__IO uint16_t epp3;
} usd_type;
/**
* @}
*/
#define FLASH ((flash_type *) FLASH_REG_BASE)
#define USD ((usd_type *) USD_BASE)
/** @defgroup FLASH_exported_functions
* @{
*/
flag_status flash_flag_get(uint32_t flash_flag);
void flash_flag_clear(uint32_t flash_flag);
flash_status_type flash_operation_status_get(void);
flash_status_type flash_operation_wait_for(uint32_t time_out);
void flash_unlock(void);
void flash_lock(void);
flash_status_type flash_sector_erase(uint32_t sector_address);
flash_status_type flash_internal_all_erase(void);
flash_status_type flash_user_system_data_erase(void);
flash_status_type flash_word_program(uint32_t address, uint32_t data);
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
flash_status_type flash_epp_set(uint32_t *sector_bits);
void flash_epp_status_get(uint32_t *sector_bits);
flash_status_type flash_fap_enable(confirm_state new_state);
flag_status flash_fap_status_get(void);
flash_status_type flash_fap_high_level_enable(confirm_state new_state);
flag_status flash_fap_high_level_status_get(void);
flash_status_type flash_ssb_set(uint8_t usd_ssb);
uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
flag_status flash_slib_state_get(void);
uint16_t flash_slib_start_sector_get(void);
uint16_t flash_slib_inststart_sector_get(void);
uint16_t flash_slib_end_sector_get(void);
uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt);
void flash_boot_memory_extension_mode_enable(void);
flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t inst_start_sector);
flag_status flash_extension_memory_slib_state_get(void);
uint16_t flash_em_slib_inststart_sector_get(void);
void flash_low_power_mode_enable(confirm_state new_state);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_gpio.h
+663
View File
@@ -0,0 +1,663 @@
/**
**************************************************************************
* @file at32f421_gpio.h
* @brief at32f421 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/**
porta iomux table
--------------------------------------------------------------------------------------------------------------------------------
pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 |
--------------------------------------------------------------------------------------------------------------------------------
pa0 | | usart2_cts | | | i2c2_scl | tmr1_etr | | comp_out |
--------------------------------------------------------------------------------------------------------------------------------
pa1 | eventout | usart2_rts | | | i2c2_sda | tmr15_ch1c | | |
--------------------------------------------------------------------------------------------------------------------------------
pa2 | tmr15_ch1 | usart2_tx | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa3 | tmr15_ch2 | usart2_rx | | | | i2s2_mck | | |
--------------------------------------------------------------------------------------------------------------------------------
pa4 | spi1_nss | usart2_ck | | | tmr14_ch1 | | | |
| i2s1_ws | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa5 | spi1_sck | | | | | | | |
| i2s1_ck | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa6 | spi1_miso | tmr3_ch1 | tmr1_bkin | i2s2_mck | | tmr16_ch1 | eventout | comp_out |
| i2s1_mck | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa7 | spi1_mosi | tmr3_ch2 | tmr1_ch1c | | tmr14_ch1 | tmr17_ch1 | eventout | |
| i2s1_sd | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa8 | clkout | usart1_ck | tmr1_ch1 | eventout | usart2_tx | | | i2c2_scl |
--------------------------------------------------------------------------------------------------------------------------------
pa9 | tmr15_bkin | usart1_tx | tmr1_ch2 | | i2c1_scl | clkout | | i2c2_smba |
--------------------------------------------------------------------------------------------------------------------------------
pa10 | tmr17_bkin | usart1_rx | tmr1_ch3 | | i2c1_sda | | | |
--------------------------------------------------------------------------------------------------------------------------------
pa11 | eventout | usart1_cts | tmr1_ch4 | | i2c1_smba | i2c2_scl | | comp_out |
----------------------------- --------------------------------------------------------------------------------------------------
pa12 | eventout | usart1_rts | tmr1_etr | | | i2c2_sda | | |
--------------------------------------------------------------------------------------------------------------------------------
pa13 | swdio | ir_out | | | | | spi2_miso | |
| | | | | | | i2s2_mck | |
--------------------------------------------------------------------------------------------------------------------------------
pa14 | swclk | usart2_tx | | | | | spi2_mosi | |
| | | | | | | i2s2_sd | |
--------------------------------------------------------------------------------------------------------------------------------
pa15 | spi1_nss | usart2_rx | | | | | spi2_nss | |
| i2s1_ws | | | eventout | | | i2s2_ws | |
--------------------------------------------------------------------------------------------------------------------------------
*/
/**
portb iomux table
--------------------------------------------------------------------------------------------------------------------------------
pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 |
--------------------------------------------------------------------------------------------------------------------------------
pb0 | eventout | tmr3_ch3 | tmr1_ch2c | usart2_rx | | | i2s1_mck | |
--------------------------------------------------------------------------------------------------------------------------------
pb1 | tmr14_ch1 | tmr3_ch4 | tmr1_ch3c | | | | spi2_sck | |
| | | | | | | i2s2_ck | |
--------------------------------------------------------------------------------------------------------------------------------
pb2 | | | tmr3_etr | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb3 | spi1_sck | eventout | | | | | spi2_sck | |
| i2s1_ck | | | | | | i2s2_ck | |
--------------------------------------------------------------------------------------------------------------------------------
pb4 | spi1_miso | tmr3_ch1 | eventout | | | tmr17_bkin | spi2_miso | i2c2_sda |
| i2s1_mck | | | | | | spi2_mck | |
--------------------------------------------------------------------------------------------------------------------------------
pb5 | spi1_mosi | tmr3_ch2 | tmr16_bkin | i2c1_smba | | | spi2_mosi | |
| i2s1_sd | | | | | | i2s2_sd | |
--------------------------------------------------------------------------------------------------------------------------------
pb6 | usart1_tx | i2c1_scl | tmr16_ch1c | | | | i2s1_mck | |
--------------------------------------------------------------------------------------------------------------------------------
pb7 | usart1_rx | i2c1_sda | tmr17_ch1c | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb8 | | i2c1_scl | tmr16_ch1 | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb9 | ir_out | i2c1_sda | tmr17_ch1 | eventout | | | i2s1_mck | spi2_nss |
| | | | | | | | i2s2_ws |
--------------------------------------------------------------------------------------------------------------------------------
pb10 | | i2c2_scl | | | | | | spi2_sck |
| | | | | | | | i2s2_ck |
--------------------------------------------------------------------------------------------------------------------------------
pb11 | eventout | i2c2_sda | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb12 | spi2_nss | eventout | tmr1_bkin | | | tmr15_bkin | | i2c2_smba |
| i2s2_ws | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb13 | spi2_sck | | tmr1_ch1c | | | i2c2_scl | | |
| i2s2_ck | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb14 | spi2_miso | tmr15_ch1 | tmr1_ch2c | | | i2c2_sda | | |
| i2s2_mck | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pb15 | spi2_mosi | tmr15_ch2 | tmr1_ch3c | tmr15_ch1c | | | | |
| i2s2_sd | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
*/
/**
portf iomux table
--------------------------------------------------------------------------------------------------------------------------------
pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 |
--------------------------------------------------------------------------------------------------------------------------------
pf0 | | i2c1_sda | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pf0 | | i2c1_scl | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pf6 | i2c2_scl | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
pf7 | i2c2_sda | | | | | | | |
--------------------------------------------------------------------------------------------------------------------------------
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_GPIO_H
#define __AT32F421_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_pins_number_definition
* @{
*/
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
/**
* @}
*/
/** @defgroup GPIO_exported_types
* @{
*/
/**
* @brief gpio mode select
*/
typedef enum
{
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
} gpio_mode_type;
/**
* @brief gpio output drive strength select
*/
typedef enum
{
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
} gpio_drive_type;
/**
* @brief gpio output type
*/
typedef enum
{
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
} gpio_output_type;
/**
* @brief gpio pull type
*/
typedef enum
{
GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
GPIO_PULL_UP = 0x01, /*!< pull-up */
GPIO_PULL_DOWN = 0x02 /*!< pull-down */
} gpio_pull_type;
/**
* @brief gpio init type
*/
typedef struct
{
uint32_t gpio_pins; /*!< pins number selection */
gpio_output_type gpio_out_type; /*!< output type selection */
gpio_pull_type gpio_pull; /*!< pull type selection */
gpio_mode_type gpio_mode; /*!< mode selection */
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
} gpio_init_type;
/**
* @brief gpio pins source type
*/
typedef enum
{
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
} gpio_pins_source_type;
/**
* @brief gpio muxing function selection type
*/
typedef enum
{
GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
} gpio_mux_sel_type;
/**
* @brief type define gpio register all
*/
typedef struct
{
/**
* @brief gpio mode register, offset:0x00
*/
union
{
__IO uint32_t cfgr;
struct
{
__IO uint32_t iomc0 : 2; /* [1:0] */
__IO uint32_t iomc1 : 2; /* [3:2] */
__IO uint32_t iomc2 : 2; /* [5:4] */
__IO uint32_t iomc3 : 2; /* [7:6] */
__IO uint32_t iomc4 : 2; /* [9:8] */
__IO uint32_t iomc5 : 2; /* [11:10] */
__IO uint32_t iomc6 : 2; /* [13:12] */
__IO uint32_t iomc7 : 2; /* [15:14] */
__IO uint32_t iomc8 : 2; /* [17:16] */
__IO uint32_t iomc9 : 2; /* [19:18] */
__IO uint32_t iomc10 : 2; /* [21:20] */
__IO uint32_t iomc11 : 2; /* [23:22] */
__IO uint32_t iomc12 : 2; /* [25:24] */
__IO uint32_t iomc13 : 2; /* [27:26] */
__IO uint32_t iomc14 : 2; /* [29:28] */
__IO uint32_t iomc15 : 2; /* [31:30] */
} cfgr_bit;
};
/**
* @brief gpio output type register, offset:0x04
*/
union
{
__IO uint32_t omode;
struct
{
__IO uint32_t om0 : 1; /* [0] */
__IO uint32_t om1 : 1; /* [1] */
__IO uint32_t om2 : 1; /* [2] */
__IO uint32_t om3 : 1; /* [3] */
__IO uint32_t om4 : 1; /* [4] */
__IO uint32_t om5 : 1; /* [5] */
__IO uint32_t om6 : 1; /* [6] */
__IO uint32_t om7 : 1; /* [7] */
__IO uint32_t om8 : 1; /* [8] */
__IO uint32_t om9 : 1; /* [9] */
__IO uint32_t om10 : 1; /* [10] */
__IO uint32_t om11 : 1; /* [11] */
__IO uint32_t om12 : 1; /* [12] */
__IO uint32_t om13 : 1; /* [13] */
__IO uint32_t om14 : 1; /* [14] */
__IO uint32_t om15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} omode_bit;
};
/**
* @brief gpio output driver register, offset:0x08
*/
union
{
__IO uint32_t odrvr;
struct
{
__IO uint32_t odrv0 : 2; /* [1:0] */
__IO uint32_t odrv1 : 2; /* [3:2] */
__IO uint32_t odrv2 : 2; /* [5:4] */
__IO uint32_t odrv3 : 2; /* [7:6] */
__IO uint32_t odrv4 : 2; /* [9:8] */
__IO uint32_t odrv5 : 2; /* [11:10] */
__IO uint32_t odrv6 : 2; /* [13:12] */
__IO uint32_t odrv7 : 2; /* [15:14] */
__IO uint32_t odrv8 : 2; /* [17:16] */
__IO uint32_t odrv9 : 2; /* [19:18] */
__IO uint32_t odrv10 : 2; /* [21:20] */
__IO uint32_t odrv11 : 2; /* [23:22] */
__IO uint32_t odrv12 : 2; /* [25:24] */
__IO uint32_t odrv13 : 2; /* [27:26] */
__IO uint32_t odrv14 : 2; /* [29:28] */
__IO uint32_t odrv15 : 2; /* [31:30] */
} odrvr_bit;
};
/**
* @brief gpio pull up/down register, offset:0x0C
*/
union
{
__IO uint32_t pull;
struct
{
__IO uint32_t pull0 : 2; /* [1:0] */
__IO uint32_t pull1 : 2; /* [3:2] */
__IO uint32_t pull2 : 2; /* [5:4] */
__IO uint32_t pull3 : 2; /* [7:6] */
__IO uint32_t pull4 : 2; /* [9:8] */
__IO uint32_t pull5 : 2; /* [11:10] */
__IO uint32_t pull6 : 2; /* [13:12] */
__IO uint32_t pull7 : 2; /* [15:14] */
__IO uint32_t pull8 : 2; /* [17:16] */
__IO uint32_t pull9 : 2; /* [19:18] */
__IO uint32_t pull10 : 2; /* [21:20] */
__IO uint32_t pull11 : 2; /* [23:22] */
__IO uint32_t pull12 : 2; /* [25:24] */
__IO uint32_t pull13 : 2; /* [27:26] */
__IO uint32_t pull14 : 2; /* [29:28] */
__IO uint32_t pull15 : 2; /* [31:30] */
} pull_bit;
};
/**
* @brief gpio input data register, offset:0x10
*/
union
{
__IO uint32_t idt;
struct
{
__IO uint32_t idt0 : 1; /* [0] */
__IO uint32_t idt1 : 1; /* [1] */
__IO uint32_t idt2 : 1; /* [2] */
__IO uint32_t idt3 : 1; /* [3] */
__IO uint32_t idt4 : 1; /* [4] */
__IO uint32_t idt5 : 1; /* [5] */
__IO uint32_t idt6 : 1; /* [6] */
__IO uint32_t idt7 : 1; /* [7] */
__IO uint32_t idt8 : 1; /* [8] */
__IO uint32_t idt9 : 1; /* [9] */
__IO uint32_t idt10 : 1; /* [10] */
__IO uint32_t idt11 : 1; /* [11] */
__IO uint32_t idt12 : 1; /* [12] */
__IO uint32_t idt13 : 1; /* [13] */
__IO uint32_t idt14 : 1; /* [14] */
__IO uint32_t idt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} idt_bit;
};
/**
* @brief gpio output data register, offset:0x14
*/
union
{
__IO uint32_t odt;
struct
{
__IO uint32_t odt0 : 1; /* [0] */
__IO uint32_t odt1 : 1; /* [1] */
__IO uint32_t odt2 : 1; /* [2] */
__IO uint32_t odt3 : 1; /* [3] */
__IO uint32_t odt4 : 1; /* [4] */
__IO uint32_t odt5 : 1; /* [5] */
__IO uint32_t odt6 : 1; /* [6] */
__IO uint32_t odt7 : 1; /* [7] */
__IO uint32_t odt8 : 1; /* [8] */
__IO uint32_t odt9 : 1; /* [9] */
__IO uint32_t odt10 : 1; /* [10] */
__IO uint32_t odt11 : 1; /* [11] */
__IO uint32_t odt12 : 1; /* [12] */
__IO uint32_t odt13 : 1; /* [13] */
__IO uint32_t odt14 : 1; /* [14] */
__IO uint32_t odt15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} odt_bit;
};
/**
* @brief gpio scr register, offset:0x18
*/
union
{
__IO uint32_t scr;
struct
{
__IO uint32_t iosb0 : 1; /* [0] */
__IO uint32_t iosb1 : 1; /* [1] */
__IO uint32_t iosb2 : 1; /* [2] */
__IO uint32_t iosb3 : 1; /* [3] */
__IO uint32_t iosb4 : 1; /* [4] */
__IO uint32_t iosb5 : 1; /* [5] */
__IO uint32_t iosb6 : 1; /* [6] */
__IO uint32_t iosb7 : 1; /* [7] */
__IO uint32_t iosb8 : 1; /* [8] */
__IO uint32_t iosb9 : 1; /* [9] */
__IO uint32_t iosb10 : 1; /* [10] */
__IO uint32_t iosb11 : 1; /* [11] */
__IO uint32_t iosb12 : 1; /* [12] */
__IO uint32_t iosb13 : 1; /* [13] */
__IO uint32_t iosb14 : 1; /* [14] */
__IO uint32_t iosb15 : 1; /* [15] */
__IO uint32_t iocb0 : 1; /* [16] */
__IO uint32_t iocb1 : 1; /* [17] */
__IO uint32_t iocb2 : 1; /* [18] */
__IO uint32_t iocb3 : 1; /* [19] */
__IO uint32_t iocb4 : 1; /* [20] */
__IO uint32_t iocb5 : 1; /* [21] */
__IO uint32_t iocb6 : 1; /* [22] */
__IO uint32_t iocb7 : 1; /* [23] */
__IO uint32_t iocb8 : 1; /* [24] */
__IO uint32_t iocb9 : 1; /* [25] */
__IO uint32_t iocb10 : 1; /* [26] */
__IO uint32_t iocb11 : 1; /* [27] */
__IO uint32_t iocb12 : 1; /* [28] */
__IO uint32_t iocb13 : 1; /* [29] */
__IO uint32_t iocb14 : 1; /* [30] */
__IO uint32_t iocb15 : 1; /* [31] */
} scr_bit;
};
/**
* @brief gpio wpr register, offset:0x1C
*/
union
{
__IO uint32_t wpr;
struct
{
__IO uint32_t wpen0 : 1; /* [0] */
__IO uint32_t wpen1 : 1; /* [1] */
__IO uint32_t wpen2 : 1; /* [2] */
__IO uint32_t wpen3 : 1; /* [3] */
__IO uint32_t wpen4 : 1; /* [4] */
__IO uint32_t wpen5 : 1; /* [5] */
__IO uint32_t wpen6 : 1; /* [6] */
__IO uint32_t wpen7 : 1; /* [7] */
__IO uint32_t wpen8 : 1; /* [8] */
__IO uint32_t wpen9 : 1; /* [9] */
__IO uint32_t wpen10 : 1; /* [10] */
__IO uint32_t wpen11 : 1; /* [11] */
__IO uint32_t wpen12 : 1; /* [12] */
__IO uint32_t wpen13 : 1; /* [13] */
__IO uint32_t wpen14 : 1; /* [14] */
__IO uint32_t wpen15 : 1; /* [15] */
__IO uint32_t wpseq : 1; /* [16] */
__IO uint32_t reserved1 : 15;/* [31:17] */
} wpr_bit;
};
/**
* @brief gpio muxl register, offset:0x20
*/
union
{
__IO uint32_t muxl;
struct
{
__IO uint32_t muxl0 : 4; /* [3:0] */
__IO uint32_t muxl1 : 4; /* [7:4] */
__IO uint32_t muxl2 : 4; /* [11:8] */
__IO uint32_t muxl3 : 4; /* [15:12] */
__IO uint32_t muxl4 : 4; /* [19:16] */
__IO uint32_t muxl5 : 4; /* [23:20] */
__IO uint32_t muxl6 : 4; /* [27:24] */
__IO uint32_t muxl7 : 4; /* [31:28] */
} muxl_bit;
};
/**
* @brief gpio muxh register, offset:0x24
*/
union
{
__IO uint32_t muxh;
struct
{
__IO uint32_t muxh8 : 4; /* [3:0] */
__IO uint32_t muxh9 : 4; /* [7:4] */
__IO uint32_t muxh10 : 4; /* [11:8] */
__IO uint32_t muxh11 : 4; /* [15:12] */
__IO uint32_t muxh12 : 4; /* [19:16] */
__IO uint32_t muxh13 : 4; /* [23:20] */
__IO uint32_t muxh14 : 4; /* [27:24] */
__IO uint32_t muxh15 : 4; /* [31:28] */
} muxh_bit;
};
/**
* @brief gpio clr register, offset:0x28
*/
union
{
__IO uint32_t clr;
struct
{
__IO uint32_t iocb0 : 1; /* [0] */
__IO uint32_t iocb1 : 1; /* [1] */
__IO uint32_t iocb2 : 1; /* [2] */
__IO uint32_t iocb3 : 1; /* [3] */
__IO uint32_t iocb4 : 1; /* [4] */
__IO uint32_t iocb5 : 1; /* [5] */
__IO uint32_t iocb6 : 1; /* [6] */
__IO uint32_t iocb7 : 1; /* [7] */
__IO uint32_t iocb8 : 1; /* [8] */
__IO uint32_t iocb9 : 1; /* [9] */
__IO uint32_t iocb10 : 1; /* [10] */
__IO uint32_t iocb11 : 1; /* [11] */
__IO uint32_t iocb12 : 1; /* [12] */
__IO uint32_t iocb13 : 1; /* [13] */
__IO uint32_t iocb14 : 1; /* [14] */
__IO uint32_t iocb15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} clr_bit;
};
/**
* @brief gpio reserved1 register, offset:0x2C~0x38
*/
__IO uint32_t reserved1[4];
/**
* @brief gpio hdrv register, offset:0x3C
*/
union
{
__IO uint32_t hdrv;
struct
{
__IO uint32_t hdrv0 : 1; /* [0] */
__IO uint32_t hdrv1 : 1; /* [1] */
__IO uint32_t hdrv2 : 1; /* [2] */
__IO uint32_t hdrv3 : 1; /* [3] */
__IO uint32_t hdrv4 : 1; /* [4] */
__IO uint32_t hdrv5 : 1; /* [5] */
__IO uint32_t hdrv6 : 1; /* [6] */
__IO uint32_t hdrv7 : 1; /* [7] */
__IO uint32_t hdrv8 : 1; /* [8] */
__IO uint32_t hdrv9 : 1; /* [9] */
__IO uint32_t hdrv10 : 1; /* [10] */
__IO uint32_t hdrv11 : 1; /* [11] */
__IO uint32_t hdrv12 : 1; /* [12] */
__IO uint32_t hdrv13 : 1; /* [13] */
__IO uint32_t hdrv14 : 1; /* [14] */
__IO uint32_t hdrv15 : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} hdrv_bit;
};
} gpio_type;
/**
* @}
*/
#define GPIOA ((gpio_type *) GPIOA_BASE)
#define GPIOB ((gpio_type *) GPIOB_BASE)
#define GPIOC ((gpio_type *) GPIOC_BASE)
#define GPIOF ((gpio_type *) GPIOF_BASE)
/** @defgroup GPIO_exported_functions
* @{
*/
void gpio_reset(gpio_type *gpio_x);
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_input_data_read(gpio_type *gpio_x);
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_i2c.h
+400
View File
@@ -0,0 +1,400 @@
/**
**************************************************************************
* @file at32f421_i2c.h
* @brief at32f421 i2c header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_I2C_H
#define __AT32F421_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_sts1_flags_definition
* @brief i2c sts1 flag
* @{
*/
#define I2C_STARTF_FLAG ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
#define I2C_ADDR7F_FLAG ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
#define I2C_TDC_FLAG ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
#define I2C_ADDRHF_FLAG ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
#define I2C_STOPF_FLAG ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
#define I2C_RDBF_FLAG ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
#define I2C_TDBE_FLAG ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
#define I2C_OUF_FLAG ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
#define I2C_PECERR_FLAG ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
#define I2C_TMOUT_FLAG ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
#define I2C_ALERTF_FLAG ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
/**
* @}
*/
/** @defgroup I2C_sts2_flags_definition
* @brief i2c sts2 flag
* @{
*/
#define I2C_TRMODE_FLAG ((uint32_t)0x10010000) /*!< i2c transmission mode */
#define I2C_BUSYF_FLAG ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
#define I2C_DIRF_FLAG ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
#define I2C_GCADDRF_FLAG ((uint32_t)0x10100000) /*!< i2c general call address received flag */
#define I2C_DEVADDRF_FLAG ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
#define I2C_HOSTADDRF_FLAG ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
#define I2C_ADDR2_FLAG ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
* @{
*/
#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
#define I2C_EVT_INT ((uint16_t)0x0200) /*!< i2c event interrupt */
#define I2C_ERR_INT ((uint16_t)0x0100) /*!< i2c error interrupt */
/**
* @}
*/
/** @defgroup I2C_exported_types
* @{
*/
/**
* @brief i2c master receiving mode acknowledge control
*/
typedef enum
{
I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
I2C_MASTER_ACK_NEXT = 0x01 /*!< acken bit acts on the next byte */
} i2c_master_ack_type;
/**
* @brief i2c pec position set
*/
typedef enum
{
I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
I2C_PEC_POSITION_NEXT = 0x01 /*!< the next byte is pec */
} i2c_pec_position_type;
/**
* @brief i2c smbus alert pin set
*/
typedef enum
{
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
} i2c_smbus_alert_set_type;
/**
* @brief i2c smbus mode set
*/
typedef enum
{
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
} i2c_smbus_mode_set_type;
/**
* @brief i2c fast mode duty cycle
*/
typedef enum
{
I2C_FSMODE_DUTY_2_1 = 0x00, /*!< duty cycle is 2:1 in fast mode */
I2C_FSMODE_DUTY_16_9 = 0x01 /*!< duty cycle is 16:9 in fast mode */
} i2c_fsmode_duty_cycle_type;
/**
* @brief i2c address mode
*/
typedef enum
{
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
} i2c_address_mode_type;
/**
* @brief i2c address direction
*/
typedef enum
{
I2C_DIRECTION_TRANSMIT = 0x00, /*!< transmit mode */
I2C_DIRECTION_RECEIVE = 0x01 /*!< receive mode */
} i2c_direction_type;
/**
* @brief type define i2c register all
*/
typedef struct
{
/**
* @brief i2c ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t i2cen : 1; /* [0] */
__IO uint32_t permode : 1; /* [1] */
__IO uint32_t reserved1 : 1; /* [2] */
__IO uint32_t smbmode : 1; /* [3] */
__IO uint32_t arpen : 1; /* [4] */
__IO uint32_t pecen : 1; /* [5] */
__IO uint32_t gcaen : 1; /* [6] */
__IO uint32_t stretch : 1; /* [7] */
__IO uint32_t genstart : 1; /* [8] */
__IO uint32_t genstop : 1; /* [9] */
__IO uint32_t acken : 1; /* [10] */
__IO uint32_t mackctrl : 1; /* [11] */
__IO uint32_t pecten : 1; /* [12] */
__IO uint32_t smbalert : 1; /* [13] */
__IO uint32_t reserved2 : 1; /* [14] */
__IO uint32_t reset : 1; /* [15] */
__IO uint32_t reserved3 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief i2c ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t clkfreq : 8; /* [7:0] */
__IO uint32_t errien : 1; /* [8] */
__IO uint32_t evtien : 1; /* [9] */
__IO uint32_t dataien : 1; /* [10] */
__IO uint32_t dmaen : 1; /* [11] */
__IO uint32_t dmaend : 1; /* [12] */
__IO uint32_t reserved1 : 19;/* [31:13] */
} ctrl2_bit;
};
/**
* @brief i2c oaddr1 register, offset:0x08
*/
union
{
__IO uint32_t oaddr1;
struct
{
__IO uint32_t addr1 : 10;/* [9:0] */
__IO uint32_t reserved1 : 5; /* [14:10] */
__IO uint32_t addr1mode : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} oaddr1_bit;
};
/**
* @brief i2c oaddr2 register, offset:0x0C
*/
union
{
__IO uint32_t oaddr2;
struct
{
__IO uint32_t addr2en : 1; /* [0] */
__IO uint32_t addr2 : 7; /* [7:1] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} oaddr2_bit;
};
/**
* @brief i2c dt register, offset:0x10
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} dt_bit;
};
/**
* @brief i2c sts1 register, offset:0x14
*/
union
{
__IO uint32_t sts1;
struct
{
__IO uint32_t startf : 1; /* [0] */
__IO uint32_t addr7f : 1; /* [1] */
__IO uint32_t tdc : 1; /* [2] */
__IO uint32_t addrhf : 1; /* [3] */
__IO uint32_t stopf : 1; /* [4] */
__IO uint32_t reserved1 : 1; /* [5] */
__IO uint32_t rdbf : 1; /* [6] */
__IO uint32_t tdbe : 1; /* [7] */
__IO uint32_t buserr : 1; /* [8] */
__IO uint32_t arlost : 1; /* [9] */
__IO uint32_t ackfail : 1; /* [10] */
__IO uint32_t ouf : 1; /* [11] */
__IO uint32_t pecerr : 1; /* [12] */
__IO uint32_t reserved2 : 1; /* [13] */
__IO uint32_t tmout : 1; /* [14] */
__IO uint32_t alertf : 1; /* [15] */
__IO uint32_t reserved3 : 16; /* [31:16] */
} sts1_bit;
};
/**
* @brief i2c sts2 register, offset:0x18
*/
union
{
__IO uint32_t sts2;
struct
{
__IO uint32_t trmode : 1; /* [0] */
__IO uint32_t busyf : 1; /* [1] */
__IO uint32_t dirf : 1; /* [2] */
__IO uint32_t reserved1 : 1; /* [3] */
__IO uint32_t gcaddrf : 1; /* [4] */
__IO uint32_t devaddrf : 1; /* [5] */
__IO uint32_t hostaddrf : 1; /* [6] */
__IO uint32_t addr2 : 1; /* [7] */
__IO uint32_t pecval : 8; /* [15:8] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} sts2_bit;
};
/**
* @brief i2c clkctrl register, offset:0x1C
*/
union
{
__IO uint32_t clkctrl;
struct
{
__IO uint32_t speed : 12;/* [11:0] */
__IO uint32_t reserved1 : 2; /* [13:12] */
__IO uint32_t dutymode : 1; /* [14] */
__IO uint32_t speedmode : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} clkctrl_bit;
};
/**
* @brief i2c tmrise register, offset:0x20
*/
union
{
__IO uint32_t tmrise;
struct
{
__IO uint32_t risetime : 6; /* [5:0] */
__IO uint32_t reserved1 : 26;/* [31:6] */
} tmrise_bit;
};
} i2c_type;
/**
* @}
*/
#define I2C1 ((i2c_type *) I2C1_BASE)
#define I2C2 ((i2c_type *) I2C2_BASE)
/** @defgroup I2C_exported_functions
* @{
*/
void i2c_reset(i2c_type *i2c_x);
void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
void i2c_start_generate(i2c_type *i2c_x);
void i2c_stop_generate(i2c_type *i2c_x);
void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
uint8_t i2c_data_receive(i2c_type *i2c_x);
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_misc.h
+123
View File
@@ -0,0 +1,123 @@
/**
**************************************************************************
* @file at32f421_misc.h
* @brief at32f421 misc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_MISC_H
#define __AT32F421_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_vector_table_base_address
* @{
*/
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
/**
* @}
*/
/** @defgroup MISC_exported_types
* @{
*/
/**
* @brief nvic interrupt priority group
*/
typedef enum
{
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
} nvic_priority_group_type;
/**
* @brief nvic low power mode
*/
typedef enum
{
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
} nvic_lowpower_mode_type;
/**
* @brief systick clock source
*/
typedef enum
{
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
} systick_clock_source_type;
/**
* @}
*/
/** @defgroup MISC_exported_functions
* @{
*/
void nvic_system_reset(void);
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(IRQn_Type irqn);
void nvic_priority_group_config(nvic_priority_group_type priority_group);
void nvic_vector_table_set(uint32_t base, uint32_t offset);
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
void systick_clock_source_config(systick_clock_source_type source);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_pwc.h
+195
View File
@@ -0,0 +1,195 @@
/**
**************************************************************************
* @file at32f421_pwc.h
* @brief at32f421 pwc header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_PWC_H
#define __AT32F421_PWC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup PWC
* @{
*/
/** @defgroup PWC_flags_definition
* @brief pwc flag
* @{
*/
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
/**
* @}
*/
/**
* @brief pwc wakeup pin num definition
*/
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */
#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */
#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */
#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */
/** @defgroup PWC_exported_types
* @{
*/
/**
* @brief pwc pvm voltage type
*/
typedef enum
{
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
} pwc_pvm_voltage_type;
/**
* @brief pwc sleep enter type
*/
typedef enum
{
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
} pwc_sleep_enter_type;
/**
* @brief pwc deep sleep enter type
*/
typedef enum
{
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
} pwc_deep_sleep_enter_type;
/**
* @brief pwc regulator type
*/
typedef enum
{
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
} pwc_regulator_type;
/**
* @brief type define pwc register all
*/
typedef struct
{
/**
* @brief pwc ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t vrsel : 1; /* [0] */
__IO uint32_t lpsel : 1; /* [1] */
__IO uint32_t clswef : 1; /* [2] */
__IO uint32_t clsef : 1; /* [3] */
__IO uint32_t pvmen : 1; /* [4] */
__IO uint32_t pvmsel : 3; /* [7:5] */
__IO uint32_t bpwen : 1; /* [8] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} ctrl_bit;
};
/**
* @brief pwc ctrlsts register, offset:0x04
*/
union
{
__IO uint32_t ctrlsts;
struct
{
__IO uint32_t swef : 1; /* [0] */
__IO uint32_t sef : 1; /* [1] */
__IO uint32_t pvmof : 1; /* [2] */
__IO uint32_t reserved1 : 5; /* [7:3] */
__IO uint32_t swpen1 : 1; /* [8] */
__IO uint32_t swpen2 : 1; /* [9] */
__IO uint32_t reserved2 : 3; /* [12:10] */
__IO uint32_t swpen6 : 1; /* [13] */
__IO uint32_t swpen7 : 1; /* [14] */
__IO uint32_t reserved3 : 17;/* [31:15] */
} ctrlsts_bit;
};
} pwc_type;
/**
* @}
*/
#define PWC ((pwc_type *) PWC_BASE)
/** @defgroup PWC_exported_functions
* @{
*/
void pwc_reset(void);
void pwc_battery_powered_domain_access(confirm_state new_state);
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
void pwc_power_voltage_monitor_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
void pwc_flag_clear(uint32_t pwc_flag);
flag_status pwc_flag_get(uint32_t pwc_flag);
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
void pwc_standby_mode_enter(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_scfg.h
+305
View File
@@ -0,0 +1,305 @@
/**
**************************************************************************
* @file at32f421_scfg.h
* @brief at32f421 system config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_SCFG_H
#define __AT32F421_SCFG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup SCFG
* @{
*/
#define SCFG_REG(value) PERIPH_REG(SCFG_CMP_BASE, value)
#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
/** @defgroup SCFG_exported_types
* @{
*/
/**
* @brief scfg infrared modulation signal source selecting type
*/
typedef enum
{
SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */
} scfg_ir_source_type;
/**
* @brief scfg pa11 pa12 pin remap type
*/
typedef enum
{
SCFG_PA11PA12_NO_REMAP = 0x00, /* pa11 pa12 pin no remap */
SCFG_PA11PA12_TO_PA9PA10 = 0x01, /* pa11 pa12 pin remap pa9 pa10*/
} scfg_pa11pa12_remap_type;
/**
* @brief scfg adc dma channel remap type
*/
typedef enum
{
SCFG_ADC_TO_DMA_CHANNEL_1 = 0x00, /* adc config to dma channel 1 */
SCFG_ADC_TO_DMA_CHANNEL_2 = 0x01, /* adc config to dma channel 2*/
} scfg_adc_dma_remap_type;
/**
* @brief scfg usart1 tx dma channel remap type
*/
typedef enum
{
SCFG_USART1_TX_TO_DMA_CHANNEL_2 = 0x00, /* usart1 tx config to dma channel 2 */
SCFG_USART1_TX_TO_DMA_CHANNEL_4 = 0x01, /* usart1 tx config to dma channel 4 */
} scfg_usart1_tx_dma_remap_type;
/**
* @brief scfg usart1 rx dma channel remap type
*/
typedef enum
{
SCFG_USART1_RX_TO_DMA_CHANNEL_3 = 0x00, /* usart1 rx config to dma channel 3 */
SCFG_USART1_RX_TO_DMA_CHANNEL_5 = 0x01, /* usart1 rx config to dma channel 5 */
} scfg_usart1_rx_dma_remap_type;
/**
* @brief scfg tmr16 dma channel remap type
*/
typedef enum
{
SCFG_TMR16_TO_DMA_CHANNEL_3 = 0x00, /* tmr16 config to dma channel 3 */
SCFG_TMR16_TO_DMA_CHANNEL_4 = 0x01, /* tmr16 config to dma channel 4 */
} scfg_tmr16_dma_remap_type;
/**
* @brief scfg tmr17 dma channel remap type
*/
typedef enum
{
SCFG_TMR17_TO_DMA_CHANNEL_1 = 0x00, /* tmr17 config to dma channel 1 */
SCFG_TMR17_TO_DMA_CHANNEL_2 = 0x01, /* tmr17 config to dma channel 2 */
} scfg_tmr17_dma_remap_type;
/**
* @brief scfg infrared output polarity selecting type
*/
typedef enum
{
SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
} scfg_ir_polarity_type;
/**
* @brief scfg memory address mapping selecting type
*/
typedef enum
{
SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
} scfg_mem_map_type;
/**
* @brief scfg pin source type
*/
typedef enum
{
SCFG_PINS_SOURCE0 = 0x00,
SCFG_PINS_SOURCE1 = 0x01,
SCFG_PINS_SOURCE2 = 0x02,
SCFG_PINS_SOURCE3 = 0x03,
SCFG_PINS_SOURCE4 = 0x04,
SCFG_PINS_SOURCE5 = 0x05,
SCFG_PINS_SOURCE6 = 0x06,
SCFG_PINS_SOURCE7 = 0x07,
SCFG_PINS_SOURCE8 = 0x08,
SCFG_PINS_SOURCE9 = 0x09,
SCFG_PINS_SOURCE10 = 0x0A,
SCFG_PINS_SOURCE11 = 0x0B,
SCFG_PINS_SOURCE12 = 0x0C,
SCFG_PINS_SOURCE13 = 0x0D,
SCFG_PINS_SOURCE14 = 0x0E,
SCFG_PINS_SOURCE15 = 0x0F
} scfg_pins_source_type;
/**
* @brief gpio port source type
*/
typedef enum
{
SCFG_PORT_SOURCE_GPIOA = 0x00,
SCFG_PORT_SOURCE_GPIOB = 0x01,
SCFG_PORT_SOURCE_GPIOC = 0x02,
SCFG_PORT_SOURCE_GPIOF = 0x05,
} scfg_port_source_type;
/**
* @brief type define system config register all
*/
typedef struct
{
/**
* @brief scfg cfg1 register, offset:0x00
*/
union
{
__IO uint32_t cfg1;
struct
{
__IO uint32_t mem_map_sel : 2; /* [1:0] */
__IO uint32_t reserved1 : 2; /* [3:2] */
__IO uint32_t pa11_12_rmp : 1; /* [4] */
__IO uint32_t ir_pol : 1; /* [5] */
__IO uint32_t ir_src_sel : 2; /* [7:6] */
__IO uint32_t adc_dma_rmp : 1; /* [8] */
__IO uint32_t usart1_tx_dma_rmp : 1; /* [9] */
__IO uint32_t usart1_rx_dma_rmp : 1; /* [10] */
__IO uint32_t tmr16_dma_rmp : 1; /* [11] */
__IO uint32_t tmr17_dma_rmp : 1; /* [12] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} cfg1_bit;
};
/**
* @brief scfg reserved1 register, offset:0x04
*/
__IO uint32_t reserved1;
/**
* @brief scfg exintc1 register, offset:0x08
*/
union
{
__IO uint32_t exintc1;
struct
{
__IO uint32_t exint0 : 4; /* [3:0] */
__IO uint32_t exint1 : 4; /* [7:4] */
__IO uint32_t exint2 : 4; /* [11:8] */
__IO uint32_t exint3 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc1_bit;
};
/**
* @brief scfg exintc2 register, offset:0x0C
*/
union
{
__IO uint32_t exintc2;
struct
{
__IO uint32_t exint4 : 4; /* [3:0] */
__IO uint32_t exint5 : 4; /* [7:4] */
__IO uint32_t exint6 : 4; /* [11:8] */
__IO uint32_t exint7 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc2_bit;
};
/**
* @brief scfg exintc3 register, offset:0x10
*/
union
{
__IO uint32_t exintc3;
struct
{
__IO uint32_t exint8 : 4; /* [3:0] */
__IO uint32_t exint9 : 4; /* [7:4] */
__IO uint32_t exint10 : 4; /* [11:8] */
__IO uint32_t exint11 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc3_bit;
};
/**
* @brief scfg exintc4 register, offset:0x14
*/
union
{
__IO uint32_t exintc4;
struct
{
__IO uint32_t exint12 : 4; /* [3:0] */
__IO uint32_t exint13 : 4; /* [7:4] */
__IO uint32_t exint14 : 4; /* [11:8] */
__IO uint32_t exint15 : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} exintc4_bit;
};
} scfg_type;
/**
* @}
*/
#define SCFG ((scfg_type *) SCFG_CMP_BASE)
/** @defgroup SCFG_exported_functions
* @{
*/
void scfg_reset(void);
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
uint8_t scfg_mem_map_get(void);
void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap);
void scfg_adc_dma_channel_remap(scfg_adc_dma_remap_type dma_channel);
void scfg_usart1_tx_dma_channel_remap(scfg_usart1_tx_dma_remap_type dma_channel);
void scfg_usart1_rx_dma_channel_remap(scfg_usart1_rx_dma_remap_type dma_channel);
void scfg_tmr16_dma_channel_remap(scfg_tmr16_dma_remap_type dma_channel);
void scfg_tmr17_dma_channel_remap(scfg_tmr17_dma_remap_type dma_channel);
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_spi.h
+496
View File
@@ -0,0 +1,496 @@
/**
**************************************************************************
* @file at32f421_spi.h
* @brief at32f421 spi header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_SPI_H
#define __AT32F421_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/**
* @defgroup SPI_I2S_flags_definition
* @brief spi i2s flag
* @{
*/
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
/**
* @}
*/
/**
* @defgroup SPI_I2S_interrupts_definition
* @brief spi i2s interrupt
* @{
*/
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
/**
* @}
*/
/** @defgroup SPI_exported_types
* @{
*/
/**
* @brief spi frame bit num type
*/
typedef enum
{
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
} spi_frame_bit_num_type;
/**
* @brief spi master/slave mode type
*/
typedef enum
{
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
} spi_master_slave_mode_type;
/**
* @brief spi clock polarity (clkpol) type
*/
typedef enum
{
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
} spi_clock_polarity_type;
/**
* @brief spi clock phase (clkpha) type
*/
typedef enum
{
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
} spi_clock_phase_type;
/**
* @brief spi cs mode type
*/
typedef enum
{
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
} spi_cs_mode_type;
/**
* @brief spi master clock frequency division type
*/
typedef enum
{
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
} spi_mclk_freq_div_type;
/**
* @brief spi transmit first bit (lsb/msb) type
*/
typedef enum
{
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
} spi_first_bit_type;
/**
* @brief spi transmission mode type
*/
typedef enum
{
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
} spi_transmission_mode_type;
/**
* @brief spi crc direction type
*/
typedef enum
{
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
} spi_crc_direction_type;
/**
* @brief spi single line bidirectional direction type
*/
typedef enum
{
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
} spi_half_duplex_direction_type;
/**
* @brief spi software cs internal level type
*/
typedef enum
{
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
} spi_software_cs_level_type;
/**
* @brief i2s audio protocol type
*/
typedef enum
{
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
} i2s_audio_protocol_type;
/**
* @brief i2s audio frequency type
*/
typedef enum
{
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
} i2s_audio_sampling_freq_type;
/**
* @brief i2s data bit num and channel bit num type
*/
typedef enum
{
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
} i2s_data_channel_format_type;
/**
* @brief i2s operation mode type
*/
typedef enum
{
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
} i2s_operation_mode_type;
/**
* @brief i2s clock polarity type
*/
typedef enum
{
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
} i2s_clock_polarity_type;
/**
* @brief spi init type
*/
typedef struct
{
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
spi_clock_phase_type clock_phase; /*!< clock phase selection */
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
} spi_init_type;
/**
* @brief i2s init type
*/
typedef struct
{
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
confirm_state mclk_output_enable; /*!< mclk_output selection */
} i2s_init_type;
/**
* @brief type define spi register all
*/
typedef struct
{
/**
* @brief spi ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t clkpha : 1; /* [0] */
__IO uint32_t clkpol : 1; /* [1] */
__IO uint32_t msten : 1; /* [2] */
__IO uint32_t mdiv_l : 3; /* [5:3] */
__IO uint32_t spien : 1; /* [6] */
__IO uint32_t ltf : 1; /* [7] */
__IO uint32_t swcsil : 1; /* [8] */
__IO uint32_t swcsen : 1; /* [9] */
__IO uint32_t ora : 1; /* [10] */
__IO uint32_t fbn : 1; /* [11] */
__IO uint32_t ntc : 1; /* [12] */
__IO uint32_t ccen : 1; /* [13] */
__IO uint32_t slbtd : 1; /* [14] */
__IO uint32_t slben : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} ctrl1_bit;
};
/**
* @brief spi ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t dmaren : 1; /* [0] */
__IO uint32_t dmaten : 1; /* [1] */
__IO uint32_t hwcsoe : 1; /* [2] */
__IO uint32_t reserved1 : 2; /* [4:3] */
__IO uint32_t errie : 1; /* [5] */
__IO uint32_t rdbfie : 1; /* [6] */
__IO uint32_t tdbeie : 1; /* [7] */
__IO uint32_t mdiv_h : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrl2_bit;
};
/**
* @brief spi sts register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rdbf : 1; /* [0] */
__IO uint32_t tdbe : 1; /* [1] */
__IO uint32_t acs : 1; /* [2] */
__IO uint32_t tuerr : 1; /* [3] */
__IO uint32_t ccerr : 1; /* [4] */
__IO uint32_t mmerr : 1; /* [5] */
__IO uint32_t roerr : 1; /* [6] */
__IO uint32_t bf : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} sts_bit;
};
/**
* @brief spi dt register, offset:0x0C
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dt_bit;
};
/**
* @brief spi cpoly register, offset:0x10
*/
union
{
__IO uint32_t cpoly;
struct
{
__IO uint32_t cpoly : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cpoly_bit;
};
/**
* @brief spi rcrc register, offset:0x14
*/
union
{
__IO uint32_t rcrc;
struct
{
__IO uint32_t rcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} rcrc_bit;
};
/**
* @brief spi tcrc register, offset:0x18
*/
union
{
__IO uint32_t tcrc;
struct
{
__IO uint32_t tcrc : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} tcrc_bit;
};
/**
* @brief spi i2sctrl register, offset:0x1C
*/
union
{
__IO uint32_t i2sctrl;
struct
{
__IO uint32_t i2scbn : 1; /* [0] */
__IO uint32_t i2sdbn : 2; /* [2:1] */
__IO uint32_t i2sclkpol : 1; /* [3] */
__IO uint32_t stdsel : 2; /* [5:4] */
__IO uint32_t reserved1 : 1; /* [6] */
__IO uint32_t pcmfssel : 1; /* [7] */
__IO uint32_t opersel : 2; /* [9:8] */
__IO uint32_t i2sen : 1; /* [10] */
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
};
/**
* @brief spi i2sclk register, offset:0x20
*/
union
{
__IO uint32_t i2sclk;
struct
{
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
__IO uint32_t i2sodd : 1; /* [8] */
__IO uint32_t i2smclkoe : 1; /* [9] */
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
};
} spi_type;
/**
* @}
*/
#define SPI1 ((spi_type *) SPI1_BASE)
#if defined (AT32F421Cx) || defined (AT32F421Kx) || defined (AT32F421Gx)
#define SPI2 ((spi_type *) SPI2_BASE)
#endif
/** @defgroup SPI_exported_functions
* @{
*/
void spi_i2s_reset(spi_type *spi_x);
void spi_default_para_init(spi_init_type* spi_init_struct);
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
void spi_crc_next_transmit(spi_type* spi_x);
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
void spi_enable(spi_type* spi_x, confirm_state new_state);
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
void i2s_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_tmr.h
+966
View File
@@ -0,0 +1,966 @@
/**
**************************************************************************
* @file at32f421_tmr.h
* @brief at32f421 tmr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_TMR_H
#define __AT32F421_TMR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup TMR
* @{
*/
/** @defgroup TMR_flags_definition
* @brief tmr flag
* @{
*/
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
/**
* @}
*/
/** @defgroup TMR_interrupt_select_type_definition
* @brief tmr interrupt select type
* @{
*/
#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
/**
* @}
*/
/** @defgroup TMR_exported_types
* @{
*/
/**
* @brief tmr clock division type
*/
typedef enum
{
TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
} tmr_clock_division_type;
/**
* @brief tmr counter mode type
*/
typedef enum
{
TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
} tmr_count_mode_type;
/**
* @brief tmr primary mode select type
*/
typedef enum
{
TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
} tmr_primary_select_type;
/**
* @brief tmr subordinate mode input select type
*/
typedef enum
{
TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
} sub_tmr_input_sel_type;
/**
* @brief tmr subordinate mode select type
*/
typedef enum
{
TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
} tmr_sub_mode_select_type;
/**
* @brief tmr encoder mode type
*/
typedef enum
{
TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
} tmr_encoder_mode_type;
/**
* @brief tmr output control mode type
*/
typedef enum
{
TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
} tmr_output_control_mode_type;
/**
* @brief tmr force output type
*/
typedef enum
{
TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
} tmr_force_output_type;
/**
* @brief tmr output channel polarity type
*/
typedef enum
{
TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
} tmr_output_polarity_type;
/**
* @brief tmr input channel polarity type
*/
typedef enum
{
TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
} tmr_input_polarity_type;
/**
* @brief tmr channel select type
*/
typedef enum
{
TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
} tmr_channel_select_type;
/**
* @brief tmr channel1 input connected type
*/
typedef enum
{
TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
} tmr_channel1_input_connected_type;
/**
* @brief tmr input channel mapped type channel direction
*/
typedef enum
{
TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
} tmr_input_direction_mapped_type;
/**
* @brief tmr input divider type
*/
typedef enum
{
TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
} tmr_channel_input_divider_type;
/**
* @brief tmr dma request source select type
*/
typedef enum
{
TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
} tmr_dma_request_source_type;
/**
* @brief tmr dma request type
*/
typedef enum
{
TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
} tmr_dma_request_type;
/**
* @brief tmr event triggered by software type
*/
typedef enum
{
TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
}tmr_event_trigger_type;
/**
* @brief tmr polarity active type
*/
typedef enum
{
TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
}tmr_polarity_active_type;
/**
* @brief tmr external signal divider type
*/
typedef enum
{
TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
}tmr_external_signal_divider_type;
/**
* @brief tmr external signal polarity type
*/
typedef enum
{
TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
}tmr_external_signal_polarity_type;
/**
* @brief tmr dma transfer length type
*/
typedef enum
{
TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
}tmr_dma_transfer_length_type;
/**
* @brief tmr dma base address type
*/
typedef enum
{
TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
}tmr_dma_address_type;
/**
* @brief tmr brk polarity type
*/
typedef enum
{
TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
}tmr_brk_polarity_type;
/**
* @brief tmr write protect level type
*/
typedef enum
{
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
}tmr_wp_level_type;
/**
* @brief tmr input remap type
*/
typedef enum
{
TMR14_GPIO = 0x00, /*!< tmr14 input remap to gpio */
TMR14_ERTCCLK = 0x01, /*!< tmr14 input remap to ertc clock */
TMR14_HEXT_DIV32 = 0x02, /*!< tmr14 input remap to hext div32*/
TMR14_CLKOUT = 0x03 /*!< tmr14 input remap to clkout */
}tmr_input_remap_type ;
/**
* @brief tmr output channel switch selection type
*/
typedef enum
{
TMR_CH_SWITCH_SELECT_EXT = 0x00, /*!< tmr output channel switch select ext pin */
TMR_CH_SWITCH_SELECT_CXORAW_OFF = 0x01, /*!< tmr output channel switch select cxoraw off signal */
}tmr_ch_switch_select_type ;
/**
* @brief tmr output config type
*/
typedef struct
{
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
confirm_state oc_idle_state; /*!< output channel idle state */
confirm_state occ_idle_state; /*!< output channel complementary idle state */
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
confirm_state oc_output_state; /*!< output channel enable */
confirm_state occ_output_state; /*!< output channel complementary enable */
} tmr_output_config_type;
/**
* @brief tmr input capture config type
*/
typedef struct
{
tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
uint8_t input_filter_value; /*!< tmr channel filter value */
} tmr_input_config_type;
/**
* @brief tmr brkdt config type
*/
typedef struct
{
uint8_t deadtime; /*!< dead-time generator setup */
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
tmr_wp_level_type wp_level; /*!< write protect configuration */
confirm_state auto_output_enable; /*!< automatic output enable */
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
confirm_state brk_enable; /*!< tmr brk enale */
} tmr_brkdt_config_type;
/**
* @brief type define tmr register all
*/
typedef struct
{
/**
* @brief tmr ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t tmren : 1; /* [0] */
__IO uint32_t ovfen : 1; /* [1] */
__IO uint32_t ovfs : 1; /* [2] */
__IO uint32_t ocmen : 1; /* [3] */
__IO uint32_t cnt_dir : 3; /* [6:4] */
__IO uint32_t prben : 1; /* [7] */
__IO uint32_t clkdiv : 2; /* [9:8] */
__IO uint32_t pmen : 1; /* [10] */
__IO uint32_t reserved1 : 21;/* [31:11] */
} ctrl1_bit;
};
/**
* @brief tmr ctrl2 register, offset:0x04
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t cbctrl : 1; /* [0] */
__IO uint32_t reserved1 : 1; /* [1] */
__IO uint32_t ccfs : 1; /* [2] */
__IO uint32_t drs : 1; /* [3] */
__IO uint32_t ptos : 3; /* [6:4] */
__IO uint32_t c1insel : 1; /* [7] */
__IO uint32_t c1ios : 1; /* [8] */
__IO uint32_t c1cios : 1; /* [9] */
__IO uint32_t c2ios : 1; /* [10] */
__IO uint32_t c2cios : 1; /* [11] */
__IO uint32_t c3ios : 1; /* [12] */
__IO uint32_t c3cios : 1; /* [13] */
__IO uint32_t c4ios : 1; /* [14] */
__IO uint32_t reserved2 : 17;/* [31:15] */
} ctrl2_bit;
};
/**
* @brief tmr smc register, offset:0x08
*/
union
{
__IO uint32_t stctrl;
struct
{
__IO uint32_t smsel : 3; /* [2:0] */
__IO uint32_t cossel : 1; /* [3] */
__IO uint32_t stis : 3; /* [6:4] */
__IO uint32_t sts : 1; /* [7] */
__IO uint32_t esf : 4; /* [11:8] */
__IO uint32_t esdiv : 2; /* [13:12] */
__IO uint32_t ecmben : 1; /* [14] */
__IO uint32_t esp : 1; /* [15] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} stctrl_bit;
};
/**
* @brief tmr die register, offset:0x0C
*/
union
{
__IO uint32_t iden;
struct
{
__IO uint32_t ovfien : 1; /* [0] */
__IO uint32_t c1ien : 1; /* [1] */
__IO uint32_t c2ien : 1; /* [2] */
__IO uint32_t c3ien : 1; /* [3] */
__IO uint32_t c4ien : 1; /* [4] */
__IO uint32_t hallien : 1; /* [5] */
__IO uint32_t tien : 1; /* [6] */
__IO uint32_t brkie : 1; /* [7] */
__IO uint32_t ovfden : 1; /* [8] */
__IO uint32_t c1den : 1; /* [9] */
__IO uint32_t c2den : 1; /* [10] */
__IO uint32_t c3den : 1; /* [11] */
__IO uint32_t c4den : 1; /* [12] */
__IO uint32_t hallde : 1; /* [13] */
__IO uint32_t tden : 1; /* [14] */
__IO uint32_t reserved1 : 17;/* [31:15] */
} iden_bit;
};
/**
* @brief tmr ists register, offset:0x10
*/
union
{
__IO uint32_t ists;
struct
{
__IO uint32_t ovfif : 1; /* [0] */
__IO uint32_t c1if : 1; /* [1] */
__IO uint32_t c2if : 1; /* [2] */
__IO uint32_t c3if : 1; /* [3] */
__IO uint32_t c4if : 1; /* [4] */
__IO uint32_t hallif : 1; /* [5] */
__IO uint32_t trgif : 1; /* [6] */
__IO uint32_t brkif : 1; /* [7] */
__IO uint32_t reserved1 : 1; /* [8] */
__IO uint32_t c1rf : 1; /* [9] */
__IO uint32_t c2rf : 1; /* [10] */
__IO uint32_t c3rf : 1; /* [11] */
__IO uint32_t c4rf : 1; /* [12] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} ists_bit;
};
/**
* @brief tmr eveg register, offset:0x14
*/
union
{
__IO uint32_t swevt;
struct
{
__IO uint32_t ovfswtr : 1; /* [0] */
__IO uint32_t c1swtr : 1; /* [1] */
__IO uint32_t c2swtr : 1; /* [2] */
__IO uint32_t c3swtr : 1; /* [3] */
__IO uint32_t c4swtr : 1; /* [4] */
__IO uint32_t hallswtr : 1; /* [5] */
__IO uint32_t trgswtr : 1; /* [6] */
__IO uint32_t brkswtr : 1; /* [7] */
__IO uint32_t reserved : 24;/* [31:8] */
} swevt_bit;
};
/**
* @brief tmr ccm1 register, offset:0x18
*/
union
{
__IO uint32_t cm1;
/**
* @brief channel mode
*/
struct
{
__IO uint32_t c1c : 2; /* [1:0] */
__IO uint32_t c1oien : 1; /* [2] */
__IO uint32_t c1oben : 1; /* [3] */
__IO uint32_t c1octrl : 3; /* [6:4] */
__IO uint32_t c1osen : 1; /* [7] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2oien : 1; /* [10] */
__IO uint32_t c2oben : 1; /* [11] */
__IO uint32_t c2octrl : 3; /* [14:12] */
__IO uint32_t c2osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm1_output_bit;
/**
* @brief input capture mode
*/
struct
{
__IO uint32_t c1c : 2; /* [1:0] */
__IO uint32_t c1idiv : 2; /* [3:2] */
__IO uint32_t c1df : 4; /* [7:4] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2idiv : 2; /* [11:10] */
__IO uint32_t c2df : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm1_input_bit;
};
/**
* @brief tmr ccm2 register, offset:0x1C
*/
union
{
__IO uint32_t cm2;
/**
* @brief channel mode
*/
struct
{
__IO uint32_t c3c : 2; /* [1:0] */
__IO uint32_t c3oien : 1; /* [2] */
__IO uint32_t c3oben : 1; /* [3] */
__IO uint32_t c3octrl : 3; /* [6:4] */
__IO uint32_t c3osen : 1; /* [7] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4oien : 1; /* [10] */
__IO uint32_t c4oben : 1; /* [11] */
__IO uint32_t c4octrl : 3; /* [14:12] */
__IO uint32_t c4osen : 1; /* [15] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm2_output_bit;
/**
* @brief input capture mode
*/
struct
{
__IO uint32_t c3c : 2; /* [1:0] */
__IO uint32_t c3idiv : 2; /* [3:2] */
__IO uint32_t c3df : 4; /* [7:4] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4idiv : 2; /* [11:10] */
__IO uint32_t c4df : 4; /* [15:12] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cm2_input_bit;
};
/**
* @brief tmr cce register, offset:0x20
*/
union
{
uint32_t cctrl;
struct
{
__IO uint32_t c1en : 1; /* [0] */
__IO uint32_t c1p : 1; /* [1] */
__IO uint32_t c1cen : 1; /* [2] */
__IO uint32_t c1cp : 1; /* [3] */
__IO uint32_t c2en : 1; /* [4] */
__IO uint32_t c2p : 1; /* [5] */
__IO uint32_t c2cen : 1; /* [6] */
__IO uint32_t c2cp : 1; /* [7] */
__IO uint32_t c3en : 1; /* [8] */
__IO uint32_t c3p : 1; /* [9] */
__IO uint32_t c3cen : 1; /* [10] */
__IO uint32_t c3cp : 1; /* [11] */
__IO uint32_t c4en : 1; /* [12] */
__IO uint32_t c4p : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} cctrl_bit;
};
/**
* @brief tmr cnt register, offset:0x24
*/
union
{
__IO uint32_t cval;
struct
{
__IO uint32_t cval : 32;/* [31:0] */
} cval_bit;
};
/**
* @brief tmr div, offset:0x28
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} div_bit;
};
/**
* @brief tmr pr register, offset:0x2C
*/
union
{
__IO uint32_t pr;
struct
{
__IO uint32_t pr : 32;/* [31:0] */
} pr_bit;
};
/**
* @brief tmr rpr register, offset:0x30
*/
union
{
__IO uint32_t rpr;
struct
{
__IO uint32_t rpr : 8; /* [7:0] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} rpr_bit;
};
/**
* @brief tmr c1dt register, offset:0x34
*/
union
{
uint32_t c1dt;
struct
{
__IO uint32_t c1dt : 32;/* [31:0] */
} c1dt_bit;
};
/**
* @brief tmr c2dt register, offset:0x38
*/
union
{
uint32_t c2dt;
struct
{
__IO uint32_t c2dt : 32;/* [31:0] */
} c2dt_bit;
};
/**
* @brief tmr c3dt register, offset:0x3C
*/
union
{
__IO uint32_t c3dt;
struct
{
__IO uint32_t c3dt : 32;/* [31:0] */
} c3dt_bit;
};
/**
* @brief tmr c4dt register, offset:0x40
*/
union
{
__IO uint32_t c4dt;
struct
{
__IO uint32_t c4dt : 32;/* [31:0] */
} c4dt_bit;
};
/**
* @brief tmr brk register, offset:0x44
*/
union
{
__IO uint32_t brk;
struct
{
__IO uint32_t dtc : 8; /* [7:0] */
__IO uint32_t wpc : 2; /* [9:8] */
__IO uint32_t fcsodis : 1; /* [10] */
__IO uint32_t fcsoen : 1; /* [11] */
__IO uint32_t brken : 1; /* [12] */
__IO uint32_t brkv : 1; /* [13] */
__IO uint32_t aoen : 1; /* [14] */
__IO uint32_t oen : 1; /* [15] */
__IO uint32_t reserved1 : 16; /* [31:16] */
} brk_bit;
};
/**
* @brief tmr dmactrl register, offset:0x48
*/
union
{
__IO uint32_t dmactrl;
struct
{
__IO uint32_t addr : 5; /* [4:0] */
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t dtb : 5; /* [12:8] */
__IO uint32_t reserved2 : 19;/* [31:13] */
} dmactrl_bit;
};
/**
* @brief tmr dmadt register, offset:0x4C
*/
union
{
__IO uint32_t dmadt;
struct
{
__IO uint32_t dmadt : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} dmadt_bit;
};
/**
* @brief tmr rmp register, offset:0x50
*/
union
{
__IO uint32_t rmp;
struct
{
__IO uint32_t tmr14_ch1_irmp : 2; /* [1:0] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} rmp_bit;
};
} tmr_type;
/**
* @}
*/
#define TMR1 ((tmr_type *) TMR1_BASE)
#define TMR3 ((tmr_type *) TMR3_BASE)
#define TMR6 ((tmr_type *) TMR6_BASE)
#define TMR14 ((tmr_type *) TMR14_BASE)
#define TMR15 ((tmr_type *) TMR15_BASE)
#define TMR16 ((tmr_type *) TMR16_BASE)
#define TMR17 ((tmr_type *) TMR17_BASE)
/** @defgroup TMR_exported_functions
* @{
*/
void tmr_reset(tmr_type *tmr_x);
void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
uint32_t tmr_counter_value_get(tmr_type *tmr_x);
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
uint32_t tmr_div_value_get(tmr_type *tmr_x);
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_output_config_type *tmr_output_struct);
void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_output_control_mode_type oc_mode);
void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
uint32_t tmr_period_value_get(tmr_type *tmr_x);
void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
uint32_t tmr_channel_value);
uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel);
void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
confirm_state new_state);
void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
tmr_channel_input_divider_type divider_factor);
void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
uint16_t filter_value);
void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
tmr_channel_input_divider_type divider_factor);
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_channel_input_divider_type divider_factor);
void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_internal_clock_set(tmr_type *tmr_x);
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_polarity_active_type oc_polarity);
void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
ic1_polarity, tmr_input_polarity_type ic2_polarity);
void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
tmr_force_output_type force_output);
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
tmr_dma_address_type dma_base_address);
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_usart.h
+373
View File
@@ -0,0 +1,373 @@
/**
**************************************************************************
* @file at32f421_usart.h
* @brief at32f421 usart header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_USART_H
#define __AT32F421_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_flags_definition
* @brief usart flag
* @{
*/
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
/**
* @}
*/
/** @defgroup USART_interrupts_definition
* @brief usart interrupt
* @{
*/
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
/**
* @}
*/
/** @defgroup USART_exported_types
* @{
*/
/**
* @brief usart parity selection type
*/
typedef enum
{
USART_PARITY_NONE = 0x00, /*!< usart no parity */
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
} usart_parity_selection_type;
/**
* @brief usart wakeup mode type
*/
typedef enum
{
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
} usart_wakeup_mode_type;
/**
* @brief usart data bit num type
*/
typedef enum
{
USART_DATA_8BITS = 0x00, /*!< usart data size is 8 bits */
USART_DATA_9BITS = 0x01 /*!< usart data size is 9 bits */
} usart_data_bit_num_type;
/**
* @brief usart break frame bit num type
*/
typedef enum
{
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
} usart_break_bit_num_type;
/**
* @brief usart phase of the clock type
*/
typedef enum
{
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
} usart_clock_phase_type;
/**
* @brief usart polarity of the clock type
*/
typedef enum
{
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
} usart_clock_polarity_type;
/**
* @brief usart last bit clock pulse type
*/
typedef enum
{
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
} usart_lbcp_type;
/**
* @brief usart stop bit num type
*/
typedef enum
{
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
} usart_stop_bit_num_type;
/**
* @brief usart hardware flow control type
*/
typedef enum
{
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
} usart_hardware_flow_control_type;
/**
* @brief type define usart register all
*/
typedef struct
{
/**
* @brief usart sts register, offset:0x00
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t perr : 1; /* [0] */
__IO uint32_t ferr : 1; /* [1] */
__IO uint32_t nerr : 1; /* [2] */
__IO uint32_t roerr : 1; /* [3] */
__IO uint32_t idlef : 1; /* [4] */
__IO uint32_t rdbf : 1; /* [5] */
__IO uint32_t tdc : 1; /* [6] */
__IO uint32_t tdbe : 1; /* [7] */
__IO uint32_t bff : 1; /* [8] */
__IO uint32_t ctscf : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} sts_bit;
};
/**
* @brief usart dt register, offset:0x04
*/
union
{
__IO uint32_t dt;
struct
{
__IO uint32_t dt : 9; /* [8:0] */
__IO uint32_t reserved1 : 23;/* [31:9] */
} dt_bit;
};
/**
* @brief usart baudr register, offset:0x08
*/
union
{
__IO uint32_t baudr;
struct
{
__IO uint32_t div : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} baudr_bit;
};
/**
* @brief usart ctrl1 register, offset:0x0C
*/
union
{
__IO uint32_t ctrl1;
struct
{
__IO uint32_t sbf : 1; /* [0] */
__IO uint32_t rm : 1; /* [1] */
__IO uint32_t ren : 1; /* [2] */
__IO uint32_t ten : 1; /* [3] */
__IO uint32_t idleien : 1; /* [4] */
__IO uint32_t rdbfien : 1; /* [5] */
__IO uint32_t tdcien : 1; /* [6] */
__IO uint32_t tdbeien : 1; /* [7] */
__IO uint32_t perrien : 1; /* [8] */
__IO uint32_t psel : 1; /* [9] */
__IO uint32_t pen : 1; /* [10] */
__IO uint32_t wum : 1; /* [11] */
__IO uint32_t dbn : 1; /* [12] */
__IO uint32_t uen : 1; /* [13] */
__IO uint32_t reserved1 : 18;/* [31:14] */
} ctrl1_bit;
};
/**
* @brief usart ctrl2 register, offset:0x10
*/
union
{
__IO uint32_t ctrl2;
struct
{
__IO uint32_t id : 4; /* [3:0] */
__IO uint32_t reserved1 : 1; /* [4] */
__IO uint32_t bfbn : 1; /* [5] */
__IO uint32_t bfien : 1; /* [6] */
__IO uint32_t reserved2 : 1; /* [7] */
__IO uint32_t lbcp : 1; /* [8] */
__IO uint32_t clkpha : 1; /* [9] */
__IO uint32_t clkpol : 1; /* [10] */
__IO uint32_t clken : 1; /* [11] */
__IO uint32_t stopbn : 2; /* [13:12] */
__IO uint32_t linen : 1; /* [14] */
__IO uint32_t trpswap : 1; /* [15] */
__IO uint32_t reserved3 : 16;/* [31:16] */
} ctrl2_bit;
};
/**
* @brief usart ctrl3 register, offset:0x14
*/
union
{
__IO uint32_t ctrl3;
struct
{
__IO uint32_t errien : 1; /* [0] */
__IO uint32_t irdaen : 1; /* [1] */
__IO uint32_t irdalp : 1; /* [2] */
__IO uint32_t slben : 1; /* [3] */
__IO uint32_t scnacken : 1; /* [4] */
__IO uint32_t scmen : 1; /* [5] */
__IO uint32_t dmaren : 1; /* [6] */
__IO uint32_t dmaten : 1; /* [7] */
__IO uint32_t rtsen : 1; /* [8] */
__IO uint32_t ctsen : 1; /* [9] */
__IO uint32_t ctscfien : 1; /* [10] */
__IO uint32_t reserved1 : 21;/* [31:11] */
} ctrl3_bit;
};
/**
* @brief usart gdiv register, offset:0x18
*/
union
{
__IO uint32_t gdiv;
struct
{
__IO uint32_t isdiv : 8; /* [7:0] */
__IO uint32_t scgt : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} gdiv_bit;
};
} usart_type;
/**
* @}
*/
#define USART1 ((usart_type *) USART1_BASE)
#define USART2 ((usart_type *) USART2_BASE)
/** @defgroup USART_exported_functions
* @{
*/
void usart_reset(usart_type* usart_x);
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
void usart_enable(usart_type* usart_x, confirm_state new_state);
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_data_transmit(usart_type* usart_x, uint16_t data);
uint16_t usart_data_receive(usart_type* usart_x);
void usart_break_send(usart_type* usart_x);
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_wdt.h
+181
View File
@@ -0,0 +1,181 @@
/**
**************************************************************************
* @file at32f421_wdt.h
* @brief at32f421 wdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_WDT_H
#define __AT32F421_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup WDT
* @{
*/
/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
/**
* @}
*/
/** @defgroup WDT_exported_types
* @{
*/
/**
* @brief wdt division value type
*/
typedef enum
{
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
} wdt_division_type;
/**
* @brief wdt cmd value type
*/
typedef enum
{
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
} wdt_cmd_value_type;
/**
* @brief type define wdt register all
*/
typedef struct
{
/**
* @brief wdt cmd register, offset:0x00
*/
union
{
__IO uint32_t cmd;
struct
{
__IO uint32_t cmd : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} cmd_bit;
};
/**
* @brief wdt div register, offset:0x04
*/
union
{
__IO uint32_t div;
struct
{
__IO uint32_t div : 3; /* [2:0] */
__IO uint32_t reserved1 : 29;/* [31:3] */
} div_bit;
};
/**
* @brief wdt rld register, offset:0x08
*/
union
{
__IO uint32_t rld;
struct
{
__IO uint32_t rld : 12;/* [11:0] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} rld_bit;
};
/**
* @brief wdt sts register, offset:0x0C
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t divf : 1; /* [0] */
__IO uint32_t rldf : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
} sts_bit;
};
} wdt_type;
/**
* @}
*/
#define WDT ((wdt_type *) WDT_BASE)
/** @defgroup WDT_exported_functions
* @{
*/
void wdt_enable(void);
void wdt_counter_reload(void);
void wdt_reload_value_set(uint16_t reload_value);
void wdt_divider_set(wdt_division_type division);
void wdt_register_write_enable( confirm_state new_state);
flag_status wdt_flag_get(uint16_t wdt_flag);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/inc/at32f421_wwdt.h
+157
View File
@@ -0,0 +1,157 @@
/**
**************************************************************************
* @file at32f421_wwdt.h
* @brief at32f421 wwdt header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_WWDT_H
#define __AT32F421_WWDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "at32f421.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @addtogroup WWDT
* @{
*/
/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
* @}
*/
/** @defgroup WWDT_exported_types
* @{
*/
/**
* @brief wwdt division type
*/
typedef enum
{
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
} wwdt_division_type;
/**
* @brief type define wwdt register all
*/
typedef struct
{
/**
* @brief wwdt ctrl register, offset:0x00
*/
union
{
__IO uint32_t ctrl;
struct
{
__IO uint32_t cnt : 7; /* [6:0] */
__IO uint32_t wwdten : 1; /* [7] */
__IO uint32_t reserved1 : 24;/* [31:8] */
} ctrl_bit;
};
/**
* @brief wwdt cfg register, offset:0x04
*/
union
{
__IO uint32_t cfg;
struct
{
__IO uint32_t win : 7; /* [6:0] */
__IO uint32_t div : 2; /* [8:7] */
__IO uint32_t rldien : 1; /* [9] */
__IO uint32_t reserved1 : 22;/* [31:10] */
} cfg_bit;
};
/**
* @brief wwdt cfg register, offset:0x08
*/
union
{
__IO uint32_t sts;
struct
{
__IO uint32_t rldf : 1; /* [0] */
__IO uint32_t reserved1 : 31;/* [31:1] */
} sts_bit;
};
} wwdt_type;
/**
* @}
*/
#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{
*/
void wwdt_reset(void);
void wwdt_divider_set(wwdt_division_type division);
void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
flag_status wwdt_interrupt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/libraries/drivers/src/at32f421_adc.c
+815
View File
@@ -0,0 +1,815 @@
/**
**************************************************************************
* @file at32f421_adc.c
* @brief contains all the functions for the adc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
#ifdef ADC_MODULE_ENABLED
/** @defgroup ADC_private_functions
* @{
*/
/**
* @brief deinitialize the adc peripheral registers to their default reset values.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_reset(adc_type *adc_x)
{
if(adc_x == ADC1)
{
crm_periph_reset(CRM_ADC1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_ADC1_PERIPH_RESET, FALSE);
}
}
/**
* @brief enable or disable the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of a/d converter.
* this parameter can be: TRUE or FALSE.
* note:after adc ready,user set adcen bit will cause ordinary conversion
* @retval none
*/
void adc_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.adcen = new_state;
}
/**
* @brief adc base default para init.
* @param sequence_mode: set the state of adc sequence mode.
* this parameter can be:TRUE or FALSE
* @param repeat_mode: set the state of adc repeat conversion mode.
* this parameter can be:TRUE or FALSE
* @param data_align: set the state of adc data alignment.
* this parameter can be one of the following values:
* - ADC_RIGHT_ALIGNMENT
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0x10)
* @retval none
*/
void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
{
adc_base_struct->sequence_mode = FALSE;
adc_base_struct->repeat_mode = FALSE;
adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
adc_base_struct->ordinary_channel_length = 1;
}
/**
* @brief initialize the adc peripheral according to the specified parameters.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param sequence_mode: set the state of adc sequence mode.
* this parameter can be:TRUE or FALSE
* @param repeat_mode: set the state of adc repeat conversion mode.
* this parameter can be:TRUE or FALSE
* @param data_align: set the state of adc data alignment.
* this parameter can be one of the following values:
* - ADC_RIGHT_ALIGNMENT
* - ADC_LEFT_ALIGNMENT
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
* this parameter can be:
* - (0x1~0x10)
* @retval none
*/
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
{
adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
}
/**
* @brief enable or disable the adc dma transfer.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of the adc dma transfer.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.ocdmaen = new_state;
}
/**
* @brief enable or disable the specified adc interrupts.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_int: specifies the adc interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - ADC_VMOR_INT
* - ADC_CCE_INT
* - ADC_PCCE_INT
* @param new_state: new state of the specified adc interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
{
if(new_state == TRUE)
{
adc_x->ctrl1 |= adc_int;
}
else if(new_state == FALSE)
{
adc_x->ctrl1 &= ~adc_int;
}
}
/**
* @brief initialize calibration register of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_calibration_init(adc_type *adc_x)
{
adc_x->ctrl2_bit.adcalinit = TRUE;
}
/**
* @brief get calibration register's initialize status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of reset calibration register status(SET or RESET).
*/
flag_status adc_calibration_init_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.adcalinit)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief start calibration process of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval none
*/
void adc_calibration_start(adc_type *adc_x)
{
adc_x->ctrl2_bit.adcal = TRUE;
}
/**
* @brief get calibration status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of calibration status(SET or RESET).
*/
flag_status adc_calibration_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.adcal)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_voltage_monitoring: choose the adc_voltage_monitoring config.
* this parameter can be one of the following values:
* - ADC_VMONITOR_SINGLE_ORDINARY
* - ADC_VMONITOR_SINGLE_PREEMPT
* - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
* - ADC_VMONITOR_ALL_ORDINARY
* - ADC_VMONITOR_ALL_PREEMPT
* - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
* - ADC_VMONITOR_NONE
* @retval none
*/
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
{
adc_x->ctrl1_bit.ocvmen = FALSE;
adc_x->ctrl1_bit.pcvmen = FALSE;
adc_x->ctrl1_bit.vmsgen = FALSE;
adc_x->ctrl1 |= adc_voltage_monitoring;
}
/**
* @brief set voltage monitoring's high and low thresholds value of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_high_threshold: voltage monitoring's high thresholds value.
* this parameter can be:
* - (0x000~0xFFF)
* @param adc_low_threshold: voltage monitoring's low thresholds value.
* this parameter can be:
* - (0x000~0xFFF)
* @retval none
*/
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
{
adc_x->vmhb_bit.vmhb = adc_high_threshold;
adc_x->vmlb_bit.vmlb = adc_low_threshold;
}
/**
* @brief select the voltage monitoring's channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @retval none
*/
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
{
adc_x->ctrl1_bit.vmcsel = adc_channel;
}
/**
* @brief set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @param adc_sequence: set rank in the ordinary group sequencer.
* this parameter must be:
* - between 1 to 16
* @param adc_sampletime: set the sampletime of adc channel.
* this parameter can be one of the following values:
* - ADC_SAMPLETIME_1_5
* - ADC_SAMPLETIME_7_5
* - ADC_SAMPLETIME_13_5
* - ADC_SAMPLETIME_28_5
* - ADC_SAMPLETIME_41_5
* - ADC_SAMPLETIME_55_5
* - ADC_SAMPLETIME_71_5
* - ADC_SAMPLETIME_239_5
* @retval none
*/
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint32_t tmp_reg;
if(adc_channel < ADC_CHANNEL_10)
{
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
if(adc_sequence >= 13)
{
tmp_reg = adc_x->osq1;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
adc_x->osq1 = tmp_reg;
}
else if(adc_sequence >= 7)
{
tmp_reg = adc_x->osq2;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
adc_x->osq2 = tmp_reg;
}
else
{
tmp_reg = adc_x->osq3;
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
adc_x->osq3 = tmp_reg;
}
}
/**
* @brief set preempt channel lenghth of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel_lenght: set the adc preempt channel lenghth.
* this parameter can be:
* - (0x1~0x4)
* @retval none
*/
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
{
adc_x->psq_bit.pclen = adc_channel_lenght - 1;
}
/**
* @brief configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel: select the channel.
* this parameter can be one of the following values:
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
* @param adc_sequence: set rank in the preempt group sequencer.
* this parameter must be:
* - between 1 to 4
* @param adc_sampletime: config the sampletime of adc channel.
* this parameter can be one of the following values:
* - ADC_SAMPLETIME_1_5
* - ADC_SAMPLETIME_7_5
* - ADC_SAMPLETIME_13_5
* - ADC_SAMPLETIME_28_5
* - ADC_SAMPLETIME_41_5
* - ADC_SAMPLETIME_55_5
* - ADC_SAMPLETIME_71_5
* - ADC_SAMPLETIME_239_5
* @retval none
*/
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
{
uint32_t tmp_reg;
uint8_t sequence_index;
if(adc_channel < ADC_CHANNEL_10)
{
tmp_reg = adc_x->spt2;
tmp_reg &= ~(0x07 << 3 * adc_channel);
tmp_reg |= adc_sampletime << 3 * adc_channel;
adc_x->spt2 = tmp_reg;
}
else
{
tmp_reg = adc_x->spt1;
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
adc_x->spt1 = tmp_reg;
}
sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
switch(sequence_index)
{
case 1:
adc_x->psq_bit.psn1 = adc_channel;
break;
case 2:
adc_x->psq_bit.psn2 = adc_channel;
break;
case 3:
adc_x->psq_bit.psn3 = adc_channel;
break;
case 4:
adc_x->psq_bit.psn4 = adc_channel;
break;
default:
break;
}
}
/**
* @brief enable or disable the ordinary channel's external trigger and
* set external trigger event of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_ordinary_trig: select the external trigger event.
* this parameter can be one of the following values:
* adc1
* - ADC12_ORDINARY_TRIG_TMR1CH1 - ADC12_ORDINARY_TRIG_TMR1CH2 - ADC12_ORDINARY_TRIG_TMR1CH3
* - ADC12_ORDINARY_TRIG_TMR3TRGOUT - ADC12_ORDINARY_TRIG_TMR15CH1 - ADC12_ORDINARY_TRIG_EXINT11 - ADC12_ORDINARY_TRIG_SOFTWARE
* @param new_state: new state of ordinary channel's external trigger.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state)
{
if(adc_ordinary_trig > 7)
{
adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7;
}
else
{
adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7;
}
adc_x->ctrl2_bit.octen = new_state;
}
/**
* @brief enable or disable the preempt channel's external trigger and
* set external trigger event of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_trig: select the external trigger event.
* this parameter can be one of the following values:
* adc1
* - ADC12_PREEMPT_TRIG_TMR1TRGOUT - ADC12_PREEMPT_TRIG_TMR1CH4
* - ADC12_PREEMPT_TRIG_TMR3CH4 - ADC12_PREEMPT_TRIG_TMR15TRGOUT - ADC12_PREEMPT_TRIG_EXINT15 - ADC12_PREEMPT_TRIG_SOFTWARE
* @param new_state: new state of preempt channel's external trigger.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state)
{
if(adc_preempt_trig > 7)
{
adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7;
}
else
{
adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7;
}
adc_x->ctrl2_bit.pcten = new_state;
}
/**
* @brief set preempt channel's conversion value offset of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_channel: select the preempt channel.
* this parameter can be one of the following values:
* - ADC_PREEMPT_CHANNEL_1
* - ADC_PREEMPT_CHANNEL_2
* - ADC_PREEMPT_CHANNEL_3
* - ADC_PREEMPT_CHANNEL_4
* @param adc_offset_value: set the adc preempt channel's conversion value offset.
* this parameter can be:
* - (0x000~0xFFF)
* @retval none
*/
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
{
switch(adc_preempt_channel)
{
case ADC_PREEMPT_CHANNEL_1:
adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_2:
adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_3:
adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
break;
case ADC_PREEMPT_CHANNEL_4:
adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
break;
default:
break;
}
}
/**
* @brief set partitioned mode channel count of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_channel_count: configure the adc partitioned mode channel count.
* this parameter can be:
* - (0x1~0x8)
* @retval none
*/
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
{
adc_x->ctrl1_bit.ocpcnt = adc_channel_count - 1;
}
/**
* @brief enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of ordinary channel's partitioned mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.ocpen = new_state;
}
/**
* @brief enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of preempt channel's partitioned mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.pcpen = new_state;
}
/**
* @brief enable or disable automatic preempt group conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of automatic preempt group conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl1_bit.pcautoen = new_state;
}
/**
* @brief enable or disable the temperature sensor and vintrv channel.
* @param new_state: new state of Internal temperature sensor and vintrv.
* this parameter can be: TRUE or FALSE.
* note:this bit is present only in adc1
* @retval none
*/
void adc_tempersensor_vintrv_enable(confirm_state new_state)
{
ADC1->ctrl2_bit.itsrven = new_state;
}
/**
* @brief enable or disable ordinary software start conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of ordinary software start conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.ocswtrg = new_state;
}
/**
* @brief get ordinary software start conversion status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of ordinary software start conversion status(SET or RESET).
*/
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.ocswtrg)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief enable or disable preempt software start conversion of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param new_state: new state of preempt software start conversion.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
{
adc_x->ctrl2_bit.pcswtrg = new_state;
}
/**
* @brief get preempt software start conversion status of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the new state of preempt software start conversion status(SET or RESET).
*/
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
{
if(adc_x->ctrl2_bit.pcswtrg)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief return the last conversion data for ordinary channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @retval the last conversion data for ordinary channel.
*/
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
{
return (uint16_t)(adc_x->odt_bit.odt);
}
/**
* @brief return the conversion data for selection preempt channel of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_preempt_channel: select the preempt channel.
* this parameter can be one of the following values:
* - ADC_PREEMPT_CHANNEL_1
* - ADC_PREEMPT_CHANNEL_2
* - ADC_PREEMPT_CHANNEL_3
* - ADC_PREEMPT_CHANNEL_4
* @retval the conversion data for selection preempt channel.
*/
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
{
uint16_t preempt_conv_data_index = 0;
switch(adc_preempt_channel)
{
case ADC_PREEMPT_CHANNEL_1:
preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
break;
case ADC_PREEMPT_CHANNEL_2:
preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
break;
case ADC_PREEMPT_CHANNEL_3:
preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
break;
case ADC_PREEMPT_CHANNEL_4:
preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
break;
default:
break;
}
return preempt_conv_data_index;
}
/**
* @brief get flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be one of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG
* - ADC_PCCE_FLAG
* - ADC_PCCS_FLAG(no interrupt associated)
* - ADC_OCCS_FLAG(no interrupt associated)
* @retval the new state of adc flag status(SET or RESET).
*/
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
{
flag_status status = RESET;
if((adc_x->sts & adc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be one of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG
* - ADC_PCCE_FLAG
* @retval the new state of adc flag status(SET or RESET).
*/
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
{
flag_status status = RESET;
switch(adc_flag)
{
case ADC_VMOR_FLAG:
if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
{
status = SET;
}
break;
case ADC_CCE_FLAG:
if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien)
{
status = SET;
}
break;
case ADC_PCCE_FLAG:
if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
{
status = SET;
}
break;
default:
break;
}
return status;
}
/**
* @brief clear flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be any combination of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG(also can clear by reading the adc_x->odt)
* - ADC_PCCE_FLAG
* - ADC_PCCS_FLAG
* - ADC_OCCS_FLAG
* @retval none
*/
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
{
adc_x->sts = ~adc_flag;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_cmp.c
+231
View File
@@ -0,0 +1,231 @@
/**
**************************************************************************
* @file at32f421_cmp.c
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CMP
* @brief CMP driver modules
* @{
*/
#ifdef CMP_MODULE_ENABLED
/** @defgroup CMP_private_functions
* @{
*/
#define CMP_CTRLSTS1_CLEAR_MASK ((uint32_t)0x00039C7C)
#define CMP_INPINPUT_CLEAR_MASK ((uint32_t)0x00000180)
#define CMP_HIGH_PULSE_CLEAR_MASK ((uint16_t)0x003F)
#define CMP_LOW_PULSE_CLEAR_MASK ((uint16_t)0x003F)
/**
* @brief reset the cmp register
* @param none
* @retval none
*/
void cmp_reset(void)
{
crm_periph_reset(CRM_CMP_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_CMP_PERIPH_RESET, FALSE);
}
/**
* @brief initialize the cmp peripheral
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION
* @param cmp_init_struct: pointer to cmp init structure
* @retval none
*/
void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct)
{
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpninvsel = cmp_init_struct->cmp_non_inverting;
CMP->ctrlsts_bit.cmpinvsel = cmp_init_struct->cmp_inverting;
CMP->ctrlsts_bit.cmpssel = cmp_init_struct->cmp_speed;
CMP->ctrlsts_bit.cmptag = cmp_init_struct->cmp_output;
CMP->ctrlsts_bit.cmpp = cmp_init_struct->cmp_polarity;
CMP->ctrlsts_bit.cmphyst = cmp_init_struct->cmp_hysteresis;
}
}
/**
* @brief fill each cmp_init_type member with its default value.
* @param cmp_init_type : pointer to a cmp_init_type structure
* which will be initialized.
* @retval none
*/
void cmp_default_para_init(cmp_init_type *cmp_init_struct)
{
/* reset cmp init structure parameters values */
cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1;
cmp_init_struct->cmp_inverting = CMP_INVERTING_1_4VREFINT;
cmp_init_struct->cmp_speed = CMP_SPEED_FAST;
cmp_init_struct->cmp_output = CMP_OUTPUT_NONE;
cmp_init_struct->cmp_polarity = CMP_POL_NON_INVERTING;
cmp_init_struct->cmp_hysteresis = CMP_HYSTERESIS_NONE;
}
/**
* @brief enable or disable cmp
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state)
{
/* cmp enable */
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpen = new_state;
}
}
/**
* @brief enable or disable cmp input shift
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_input_shift_enable(confirm_state new_state)
{
CMP->ctrlsts_bit.cmpis = new_state;
}
/**
* @brief get cmp output value
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @retval cmp output value
*/
uint32_t cmp_output_value_get(cmp_sel_type cmp_sel)
{
uint32_t cmpout = 0x0;
if(cmp_sel == CMP1_SELECTION)
{
cmpout = CMP->ctrlsts_bit.cmpvalue;
}
/* return the comparator output level */
return (uint32_t)(cmpout);
}
/**
* @brief enable cmp write protect
* @param cmp_sel: to select the cmp peripheral
* this parameter only can be CMP1_SELECTION.
* @retval none
*/
void cmp_write_protect_enable(cmp_sel_type cmp_sel)
{
if(cmp_sel == CMP1_SELECTION)
{
CMP->ctrlsts_bit.cmpwp = TRUE;
}
}
/**
* @brief configure cmp glitch filter
* @param high_pulse_cnt: cmp high pulse count.
* this parameter must be a value between 0x00 and 0x3f
* @param low_pulse_cnt: cmp low pulse count.
* this parameter must be a value between 0x00 and 0x3f
* @param new_state (TRUE or FALSE)
* @retval none
*/
void cmp_filter_config(uint16_t high_pulse_cnt, uint16_t low_pulse_cnt, confirm_state new_state)
{
if (new_state != FALSE)
{
/* enable the glitch filter */
CMP->g_filter_en_bit.gfe = TRUE;
/* write to cmp high_pulse and low_pulse */
CMP->low_pulse_bit.l_pulse_cnt = low_pulse_cnt;
CMP->high_pulse_bit.h_pulse_cnt = high_pulse_cnt;
}
else
{
/* disable the glitch filter */
CMP->g_filter_en_bit.gfe = FALSE;
/* reset the h_pulse_cnt and l_pulse_cnt bits */
CMP->low_pulse_bit.l_pulse_cnt = low_pulse_cnt;
CMP->high_pulse_bit.h_pulse_cnt = high_pulse_cnt;
}
}
/**
* @brief configure cmp blanking source.
* @param blank_sel: cmp blanking source
* this parameter can be one of the following values:
* - CMP_BLANKING_NONE
* - CMP_BLANKING_TMR1_CH4
* - CMP_BLANKING_TMR3_CH3
* - CMP_BLANKING_TMR15_CH2
* - CMP_BLANKING_TMR15_CH1
* @retval none
*/
void cmp_blanking_config(cmp_blanking_type blank_sel)
{
CMP->ctrlsts_bit.cmpblanking = blank_sel;
}
/**
* @brief configure cmp scale voltage and voltage bridge
* @param scal_brg: cmp scal&brg configure
* this parameter can be one of the following values:
* - CMP_SCAL_BRG_00: vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 0v
* - CMP_SCAL_BRG_10: vrefint = 3/4 vrefint = 1/2 vrefint = 1/4 vrefint = 1.2v
* - CMP_SCAL_BRG_11: vrefint = 1.2v, 3/4 vrefint = 0.9v, 1/2 vrefint = 0.6v, 1/4 vrefint = 0.3v
* @retval none
*/
void cmp_scal_brg_config(cmp_scal_brg_type scal_brg)
{
uint32_t tmp_scal = 0, tmp_brg = 0;
tmp_scal = scal_brg >> 1;
tmp_brg = scal_brg & 0x01;
CMP->ctrlsts_bit.scalen = tmp_scal;
CMP->ctrlsts_bit.brgen = tmp_brg;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_crc.c
+208
View File
@@ -0,0 +1,208 @@
/**
**************************************************************************
* @file at32f421_crc.c
* @brief contains all the functions for the crc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
#ifdef CRC_MODULE_ENABLED
/** @defgroup CRC_private_functions
* @{
*/
/**
* @brief reset the crc data register.
* @param none
* @retval none
*/
void crc_data_reset(void)
{
/* reset crc generator */
CRC->ctrl_bit.rst = 0x1;
}
/**
* @brief compute the 32-bit crc of a given data word(32-bit).
* @param data: data word(32-bit) to compute its crc
* @retval 32-bit crc
*/
uint32_t crc_one_word_calculate(uint32_t data)
{
CRC->dt = data;
return (CRC->dt);
}
/**
* @brief compute the 32-bit crc of a given buffer of data word(32-bit).
* @param pbuffer: pointer to the buffer containing the data to be computed
* @param length: length of the buffer to be computed
* @retval 32-bit crc
*/
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
{
uint32_t index = 0;
for(index = 0; index < length; index++)
{
CRC->dt = pbuffer[index];
}
return (CRC->dt);
}
/**
* @brief return the current crc value.
* @param none
* @retval 32-bit crc
*/
uint32_t crc_data_get(void)
{
return (CRC->dt);
}
/**
* @brief store a 8-bit data in the common data register.
* @param cdt_value: 8-bit value to be stored in the common data register
* @retval none
*/
void crc_common_data_set(uint8_t cdt_value)
{
CRC->cdt_bit.cdt = cdt_value;
}
/**
* @brief return the 8-bit data stored in the common data register
* @param none
* @retval 8-bit value of the common data register
*/
uint8_t crc_common_data_get(void)
{
return (CRC->cdt_bit.cdt);
}
/**
* @brief set the 32-bit initial data of crc
* @param value: initial data
* @retval none
*/
void crc_init_data_set(uint32_t value)
{
CRC->idt = value;
}
/**
* @brief control the reversal of the bit order in the input data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_INPUT_NO_AFFECTE
* - CRC_REVERSE_INPUT_BY_BYTE
* - CRC_REVERSE_INPUT_BY_HALFWORD
* - CRC_REVERSE_INPUT_BY_WORD
* @retval none.
*/
void crc_reverse_input_data_set(crc_reverse_input_type value)
{
CRC->ctrl_bit.revid = value;
}
/**
* @brief control the reversal of the bit order in the output data
* @param value
* this parameter can be one of the following values:
* - CRC_REVERSE_OUTPUT_NO_AFFECTE
* - CRC_REVERSE_OUTPUT_DATA
* @retval none.
*/
void crc_reverse_output_data_set(crc_reverse_output_type value)
{
CRC->ctrl_bit.revod = value;
}
/**
* @brief config crc polynomial value
* @param value
* 32-bit new data of crc poly value
* @retval none.
*/
void crc_poly_value_set(uint32_t value)
{
CRC->poly = value;
}
/**
* @brief return crc polynomial value
* @param none
* @retval 32-bit value of the polynomial value.
*/
uint32_t crc_poly_value_get(void)
{
return (CRC->poly);
}
/**
* @brief config crc polynomial data size
* @param size
* this parameter can be one of the following values:
* - CRC_POLY_SIZE_32B
* - CRC_POLY_SIZE_16B
* - CRC_POLY_SIZE_8B
* - CRC_POLY_SIZE_7B
* @retval none.
*/
void crc_poly_size_set(crc_poly_size_type size)
{
CRC->ctrl_bit.poly_size = size;
}
/**
* @brief return crc polynomial data size
* @param none
* @retval polynomial data size.
*/
crc_poly_size_type crc_poly_size_get(void)
{
return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_crm.c
+940
View File
@@ -0,0 +1,940 @@
/**
**************************************************************************
* @file at32f421_crm.c
* @brief contains all the functions for the crm firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup CRM
* @brief CRM driver modules
* @{
*/
#ifdef CRM_MODULE_ENABLED
/** @defgroup CRM_private_functions
* @{
*/
/**
* @brief reset the crm register
* @param none
* @retval none
*/
void crm_reset(void)
{
/* reset the crm clock configuration to the default reset state(for debug purpose) */
/* set hicken bit */
CRM->ctrl_bit.hicken = TRUE;
/* wait hick stable */
while(CRM->ctrl_bit.hickstbl != SET);
/* hick used as system clock */
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
/* reset pllfr, pllms, pllns and pllfref bits */
CRM->pll = (0x00001F10U);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0x00100000;
/* disable all interrupts enable and clear pending bits */
CRM->clkint = 0x009F0000;
}
/**
* @brief enable or disable crm low speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_lext_bypass(confirm_state new_state)
{
CRM->bpdc_bit.lextbyps = new_state;
}
/**
* @brief enable or disable crm high speed external crystal bypass
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_hext_bypass(confirm_state new_state)
{
CRM->ctrl_bit.hextbyps = new_state;
}
/**
* @brief get crm flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_HICK_STABLE_FLAG
* - CRM_HEXT_STABLE_FLAG
* - CRM_PLL_STABLE_FLAG
* - CRM_LEXT_STABLE_FLAG
* - CRM_LICK_STABLE_FLAG
* - CRM_NRST_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_flag_get(uint32_t flag)
{
flag_status status = RESET;
if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get crm interrupt flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_interrupt_flag_get(uint32_t flag)
{
flag_status status = RESET;
switch(flag)
{
case CRM_LICK_READY_INT_FLAG:
if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien)
{
status = SET;
}
break;
case CRM_LEXT_READY_INT_FLAG:
if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien)
{
status = SET;
}
break;
case CRM_HICK_READY_INT_FLAG:
if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien)
{
status = SET;
}
break;
case CRM_HEXT_READY_INT_FLAG:
if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien)
{
status = SET;
}
break;
case CRM_PLL_READY_INT_FLAG:
if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien)
{
status = SET;
}
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden)
{
status = SET;
}
break;
}
return status;
}
/**
* @brief wait for hext stable
* @param none
* @retval error_status (ERROR or SUCCESS)
*/
error_status crm_hext_stable_wait(void)
{
uint32_t stable_cnt = 0;
error_status status = ERROR;
while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
{
stable_cnt ++;
}
if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
return status;
}
/**
* @brief set the hick trimming value
* @param trim_value (0x00~0x3F)
* @retval none
*/
void crm_hick_clock_trimming_set(uint8_t trim_value)
{
CRM->ctrl_bit.hicktrim = trim_value;
}
/**
* @brief set the crm calibration value
* @param cali_value (0x00~0xFF)
* @retval none
*/
void crm_hick_clock_calibration_set(uint8_t cali_value)
{
/* enable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x5A;
/* write hick calibration value */
CRM->ctrl_bit.hickcal = cali_value;
/* disable write hick calibration */
CRM->misc1_bit.hickcal_key = 0x0;
}
/**
* @brief enable or disable the peripheral clock
* @param value
* this parameter can be one of the following values:
* - CRM_DMA1_PERIPH_CLOCK - CRM_CRC_PERIPH_CLOCK - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK
* - CRM_GPIOC_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_SCFG_PERIPH_CLOCK - CRM_CMP_PERIPH_CLOCK
* - CRM_ADC1_PERIPH_CLOCK - CRM_TMR1_PERIPH_CLOCK - CRM_SPI1_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK
* - CRM_TMR15_PERIPH_CLOCK - CRM_TMR16_PERIPH_CLOCK - CRM_TMR17_PERIPH_CLOCK - CRM_TMR3_PERIPH_CLOCK
* - CRM_TMR6_PERIPH_CLOCK - CRM_TMR14_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK - CRM_SPI2_PERIPH_CLOCK
* - CRM_USART2_PERIPH_CLOCK - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
{
/* enable periph clock */
if(TRUE == new_state)
{
CRM_REG(value) |= CRM_REG_BIT(value);
}
/* disable periph clock */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral reset
* @param value
* this parameter can be one of the following values:
* - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET - CRM_GPIOC_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET
* - CRM_SCFG_PERIPH_RESET - CRM_CMP_PERIPH_RESET - CRM_EXINT_PERIPH_RESET - CRM_ADC1_PERIPH_RESET
* - CRM_TMR1_PERIPH_RESET - CRM_SPI1_PERIPH_RESET - CRM_USART1_PERIPH_RESET - CRM_TMR15_PERIPH_RESET
* - CRM_TMR16_PERIPH_RESET - CRM_TMR17_PERIPH_RESET - CRM_TMR3_PERIPH_RESET - CRM_TMR6_PERIPH_RESET
* - CRM_TMR14_PERIPH_RESET - CRM_WWDT_PERIPH_RESET - CRM_SPI2_PERIPH_RESET - CRM_USART2_PERIPH_RESET
* - CRM_I2C1_PERIPH_RESET - CRM_I2C2_PERIPH_RESET - CRM_PWC_PERIPH_RESET
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
{
/* enable periph reset */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable periph reset */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the peripheral clock in sleep mode
* @param value
* this parameter can be one of the following values:
* - CRM_SRAM_PERIPH_CLOCK_SLEEP_MODE
* - CRM_FLASH_PERIPH_CLOCK_SLEEP_MODE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_periph_sleep_mode_clock_enable(crm_periph_clock_sleepmd_type value, confirm_state new_state)
{
/* enable periph clock in sleep mode */
if(new_state == TRUE)
{
CRM_REG(value) |= (CRM_REG_BIT(value));
}
/* disable perph clock in sleep mode */
else
{
CRM_REG(value) &= ~(CRM_REG_BIT(value));
}
}
/**
* @brief enable or disable the crm clock source
* @param source
* this parameter can be one of the following values:
* - CRM_CLOCK_SOURCE_HICK
* - CRM_CLOCK_SOURCE_HEXT
* - CRM_CLOCK_SOURCE_PLL
* - CRM_CLOCK_SOURCE_LEXT
* - CRM_CLOCK_SOURCE_LICK
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
{
switch(source)
{
case CRM_CLOCK_SOURCE_HICK:
CRM->ctrl_bit.hicken = new_state;
break;
case CRM_CLOCK_SOURCE_HEXT:
CRM->ctrl_bit.hexten = new_state;
break;
case CRM_CLOCK_SOURCE_PLL:
CRM->ctrl_bit.pllen = new_state;
break;
case CRM_CLOCK_SOURCE_LEXT:
CRM->bpdc_bit.lexten = new_state;
break;
case CRM_CLOCK_SOURCE_LICK:
CRM->ctrlsts_bit.licken = new_state;
break;
default:
break;
}
}
/**
* @brief clear the crm reset flags
* @param flag
* this parameter can be one of the following values:
* reset flag:
* - CRM_NRST_RESET_FLAG
* - CRM_POR_RESET_FLAG
* - CRM_SW_RESET_FLAG
* - CRM_WDT_RESET_FLAG
* - CRM_WWDT_RESET_FLAG
* - CRM_LOWPOWER_RESET_FLAG
* - CRM_ALL_RESET_FLAG
* interrupt flag:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval none
*/
void crm_flag_clear(uint32_t flag)
{
switch(flag)
{
case CRM_NRST_RESET_FLAG:
case CRM_POR_RESET_FLAG:
case CRM_SW_RESET_FLAG:
case CRM_WDT_RESET_FLAG:
case CRM_WWDT_RESET_FLAG:
case CRM_LOWPOWER_RESET_FLAG:
case CRM_ALL_RESET_FLAG:
CRM->ctrlsts_bit.rstfc = TRUE;
while(CRM->ctrlsts_bit.rstfc == TRUE);
break;
case CRM_LICK_READY_INT_FLAG:
CRM->clkint_bit.lickstblfc = TRUE;
break;
case CRM_LEXT_READY_INT_FLAG:
CRM->clkint_bit.lextstblfc = TRUE;
break;
case CRM_HICK_READY_INT_FLAG:
CRM->clkint_bit.hickstblfc = TRUE;
break;
case CRM_HEXT_READY_INT_FLAG:
CRM->clkint_bit.hextstblfc = TRUE;
break;
case CRM_PLL_READY_INT_FLAG:
CRM->clkint_bit.pllstblfc = TRUE;
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
CRM->clkint_bit.cfdfc = TRUE;
break;
default:
break;
}
}
/**
* @brief select ertc clock
* @param value
* this parameter can be one of the following values:
* - CRM_ERTC_CLOCK_LEXT
* - CRM_ERTC_CLOCK_LICK
* - CRM_ERTC_CLOCK_HEXT_DIV
* @retval none
*/
void crm_ertc_clock_select(crm_ertc_clock_type value)
{
CRM->bpdc_bit.ertcsel = value;
}
/**
* @brief enable or disable ertc
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_ertc_clock_enable(confirm_state new_state)
{
CRM->bpdc_bit.ertcen = new_state;
}
/**
* @brief set crm ahb division
* @param value
* this parameter can be one of the following values:
* - CRM_AHB_DIV_1
* - CRM_AHB_DIV_2
* - CRM_AHB_DIV_4
* - CRM_AHB_DIV_8
* - CRM_AHB_DIV_16
* - CRM_AHB_DIV_64
* - CRM_AHB_DIV_128
* - CRM_AHB_DIV_256
* - CRM_AHB_DIV_512
* @retval none
*/
void crm_ahb_div_set(crm_ahb_div_type value)
{
CRM->cfg_bit.ahbdiv = value;
}
/**
* @brief set crm apb1 division
* @note the maximum frequency of APB1/APB2 clock is 120 MHz
* @param value
* this parameter can be one of the following values:
* - CRM_APB1_DIV_1
* - CRM_APB1_DIV_2
* - CRM_APB1_DIV_4
* - CRM_APB1_DIV_8
* - CRM_APB1_DIV_16
* @retval none
*/
void crm_apb1_div_set(crm_apb1_div_type value)
{
CRM->cfg_bit.apb1div = value;
}
/**
* @brief set crm apb2 division
* @note the maximum frequency of APB1/APB2 clock is 120 MHz
* @param value
* this parameter can be one of the following values:
* - CRM_APB2_DIV_1
* - CRM_APB2_DIV_2
* - CRM_APB2_DIV_4
* - CRM_APB2_DIV_8
* - CRM_APB2_DIV_16
* @retval none
*/
void crm_apb2_div_set(crm_apb2_div_type value)
{
CRM->cfg_bit.apb2div = value;
}
/**
* @brief set crm adc division
* @param value
* this parameter can be one of the following values:
* - CRM_ADC_DIV_2
* - CRM_ADC_DIV_4
* - CRM_ADC_DIV_6
* - CRM_ADC_DIV_8
* - CRM_ADC_DIV_12
* - CRM_ADC_DIV_16
* @retval none
*/
void crm_adc_clock_div_set(crm_adc_div_type div_value)
{
CRM->cfg_bit.adcdiv_l = div_value & 0x03;
CRM->cfg_bit.adcdiv_h = (div_value >> 2) & 0x01;
}
/**
* @brief enable or disable clock failure detection
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_clock_failure_detection_enable(confirm_state new_state)
{
CRM->ctrl_bit.cfden = new_state;
}
/**
* @brief battery powered domain software reset
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_battery_powered_domain_reset(confirm_state new_state)
{
CRM->bpdc_bit.bpdrst = new_state;
}
/**
* @brief config crm pll
* @param clock_source
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* - CRM_PLL_SOURCE_HEXT_DIV
* @param mult_value (CRM_PLL_MULT_2~64)
* @retval none
*/
void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mult_value)
{
uint32_t pllrcfreq = 0;
crm_pll_fref_type pllfref = CRM_PLL_FREF_4M;
/* config pll clock source */
if(clock_source == CRM_PLL_SOURCE_HICK)
{
CRM->cfg_bit.pllrcs = FALSE;
pllrcfreq = (HICK_VALUE / 2);
CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
}
else
{
CRM->cfg_bit.pllrcs = TRUE;
if(CRM_PLL_SOURCE_HEXT == clock_source)
{
pllrcfreq = HEXT_VALUE;
CRM->cfg_bit.pllhextdiv = FALSE;
}
else
{
pllrcfreq = (HEXT_VALUE / 2);
CRM->cfg_bit.pllhextdiv = TRUE;
}
}
if((pllrcfreq > 3900000U) && (pllrcfreq < 5000000U))
{
pllfref = CRM_PLL_FREF_4M;
}
else if((pllrcfreq > 5200000U) && (pllrcfreq < 6250000U))
{
pllfref = CRM_PLL_FREF_6M;
}
else if((pllrcfreq > 7812500U) && (pllrcfreq < 8330000U))
{
pllfref = CRM_PLL_FREF_8M;
}
else if((pllrcfreq > 8330000U) && (pllrcfreq < 12500000U))
{
pllfref = CRM_PLL_FREF_12M;
}
else if((pllrcfreq > 15625000U) && (pllrcfreq < 20830000U))
{
pllfref = CRM_PLL_FREF_16M;
}
else if((pllrcfreq > 20830000U) && (pllrcfreq < 31255000U))
{
pllfref = CRM_PLL_FREF_25M;
}
/* config pll multiplication factor */
CRM->cfg_bit.pllmult_l = (mult_value & 0x0F);
CRM->cfg_bit.pllmult_h = ((mult_value & 0x30) >> 4);
/* config pll fref */
CRM->pll_bit.pllfref = pllfref;
}
/**
* @brief config crm pll function2, another method.
* pll_rcs_freq * pll_ns
* pll clock = --------------------------------
* pll_ms * pll_fr_n
* attemtion:
* 31 <= pll_ns <= 500
* 1 <= pll_ms <= 15
*
* pll_rcs_freq
* 2mhz <= ---------------------- <= 16mhz
* pll_ms
*
* pll_rcs_freq * pll_ns
* 500mhz <= -------------------------------- <= 1000mhz
* pll_ms
* @param clock_source
* this parameter can be one of the following values:
* - CRM_PLL_SOURCE_HICK
* - CRM_PLL_SOURCE_HEXT
* - CRM_PLL_SOURCE_HEXT_DIV
* @param pll_ns (31~500)
* @param pll_ms (1~15)
* @param pll_fr
* this parameter can be one of the following values:
* - CRM_PLL_FR_1
* - CRM_PLL_FR_2
* - CRM_PLL_FR_4
* - CRM_PLL_FR_8
* - CRM_PLL_FR_16
* - CRM_PLL_FR_32
* @retval none
*/
void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
uint16_t pll_ms, crm_pll_fr_type pll_fr)
{
/* config pll clock source */
if(clock_source == CRM_PLL_SOURCE_HICK)
{
CRM->cfg_bit.pllrcs = FALSE;
CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
}
else
{
CRM->cfg_bit.pllrcs = TRUE;
if(clock_source == CRM_PLL_SOURCE_HEXT)
{
CRM->cfg_bit.pllhextdiv = FALSE;
}
else
{
CRM->cfg_bit.pllhextdiv = TRUE;
}
}
/* config pll multiplication factor */
CRM->pll_bit.pllns = pll_ns;
CRM->pll_bit.pllms = pll_ms;
CRM->pll_bit.pllfr = pll_fr;
CRM->pll_bit.pllcfgen = TRUE;
}
/**
* @brief select system clock source
* @param value
* this parameter can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
* @retval none
*/
void crm_sysclk_switch(crm_sclk_type value)
{
CRM->cfg_bit.sclksel = value;
DUMMY_NOP();
}
/**
* @brief indicate which clock source is used as system clock
* @param none
* @retval crm_sclk
* this return can be one of the following values:
* - CRM_SCLK_HICK
* - CRM_SCLK_HEXT
* - CRM_SCLK_PLL
*/
crm_sclk_type crm_sysclk_switch_status_get(void)
{
return (crm_sclk_type)CRM->cfg_bit.sclksts;
}
/**
* @brief get crm clocks freqency
* @param clocks
* - pointer to the crm_clocks_freq structure
* @retval none
*/
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
{
uint32_t pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
uint32_t pllrcsfreq = 0, pll_ms = 0, pll_ns = 0, pll_fr = 0;
crm_sclk_type sclk_source;
static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
static const uint8_t adc_div_table[8] = {2, 4, 6, 8, 2, 12, 8, 16};
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
case CRM_SCLK_HICK:
if(((CRM->misc2_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
clocks_struct->sclk_freq = HICK_VALUE * 6;
else
clocks_struct->sclk_freq = HICK_VALUE;
break;
case CRM_SCLK_HEXT:
clocks_struct->sclk_freq = HEXT_VALUE;
break;
case CRM_SCLK_PLL:
pll_clock_source = CRM->cfg_bit.pllrcs;
if(CRM->pll_bit.pllcfgen == FALSE)
{
/* get multiplication factor */
pll_mult = CRM->cfg_bit.pllmult_l;
pll_mult_h = CRM->cfg_bit.pllmult_h;
/* process high bits */
if((pll_mult_h != 0U) || (pll_mult == 15U))
{
pll_mult += ((16U * pll_mult_h) + 1U);
}
else
{
pll_mult += 2U;
}
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
clocks_struct->sclk_freq = (HICK_VALUE >> 1) * pll_mult;
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
clocks_struct->sclk_freq = (HEXT_VALUE / 2) * pll_mult;
}
else
{
clocks_struct->sclk_freq = HEXT_VALUE * pll_mult;
}
}
}
else
{
pll_ms = CRM->pll_bit.pllms;
pll_ns = CRM->pll_bit.pllns;
pll_fr = CRM->pll_bit.pllfr;
if (pll_clock_source == 0x00)
{
/* hick divided by 2 selected as pll clock entry */
pllrcsfreq = (HICK_VALUE >> 1);
}
else
{
/* hext selected as pll clock entry */
if (CRM->cfg_bit.pllhextdiv != RESET)
{
/* hext clock divided by 2 */
pllrcsfreq = (HEXT_VALUE / 2);
}
else
{
pllrcsfreq = HEXT_VALUE;
}
}
clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * (0x1 << pll_fr)));
}
break;
default:
clocks_struct->sclk_freq = HICK_VALUE;
break;
}
/* compute sclk, ahbclk, abp1clk apb2clk and adcclk frequencies */
/* get ahb division */
temp = CRM->cfg_bit.ahbdiv;
div_value = sclk_ahb_div_table[temp];
/* ahbclk frequency */
clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
/* get apb1 division */
temp = CRM->cfg_bit.apb1div;
div_value = ahb_apb1_div_table[temp];
/* apb1clk frequency */
clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
/* get apb2 division */
temp = CRM->cfg_bit.apb2div;
div_value = ahb_apb2_div_table[temp];
/* apb2clk frequency */
clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
/* get adc division */
temp = CRM->cfg_bit.adcdiv_h;
temp = ((temp << 2) | (CRM->cfg_bit.adcdiv_l));
div_value = adc_div_table[temp];
/* adcclk clock frequency */
clocks_struct->adc_freq = clocks_struct->apb2_freq / div_value;
}
/**
* @brief set crm clkout
* @param clkout
* this parameter can be one of the following values:
* - CRM_CLKOUT_NOCLK
* - CRM_CLKOUT_LICK
* - CRM_CLKOUT_LEXT
* - CRM_CLKOUT_SCLK
* - CRM_CLKOUT_HICK
* - CRM_CLKOUT_HEXT
* - CRM_CLKOUT_PLL_DIV_2
* - CRM_CLKOUT_PLL_DIV_4
* - CRM_CLKOUT_ADC
* @retval none
*/
void crm_clock_out_set(crm_clkout_select_type clkout)
{
CRM->cfg_bit.clkout_sel = clkout & 0x7;
CRM->misc1_bit.clkout_sel = (clkout >> 3) & 0x1;
}
/**
* @brief config crm interrupt
* @param int
* this parameter can be any combination of the following values:
* - CRM_LICK_STABLE_INT
* - CRM_LEXT_STABLE_INT
* - CRM_HICK_STABLE_INT
* - CRM_HEXT_STABLE_INT
* - CRM_PLL_STABLE_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
{
if(new_state == TRUE)
CRM->clkint |= crm_int;
else
CRM->clkint &= ~crm_int;
}
/**
* @brief auto step clock switch enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
void crm_auto_step_mode_enable(confirm_state new_state)
{
if(new_state == TRUE)
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
else
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
/**
* @brief config hick divider select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK48_DIV6
* - CRM_HICK48_NODIV
* @retval none
*/
void crm_hick_divider_select(crm_hick_div_6_type value)
{
CRM->misc1_bit.hickdiv = value;
}
/**
* @brief hick as system clock frequency select
* @param value
* this parameter can be one of the following values:
* - CRM_HICK_SCLK_8MHZ
* - CRM_HICK_SCLK_48MHZ
* @retval none
*/
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
{
crm_hick_divider_select(CRM_HICK48_NODIV);
CRM->misc2_bit.hick_to_sclk = value;
}
/**
* @brief set crm clkout division
* @param clkout_div
* this parameter can be one of the following values:
* - CRM_CLKOUT_DIV_1
* - CRM_CLKOUT_DIV_2
* - CRM_CLKOUT_DIV_4
* - CRM_CLKOUT_DIV_8
* - CRM_CLKOUT_DIV_16
* - CRM_CLKOUT_DIV_64
* - CRM_CLKOUT_DIV_128
* - CRM_CLKOUT_DIV_256
* - CRM_CLKOUT_DIV_512
* @retval none
*/
void crm_clkout_div_set(crm_clkout_div_type clkout_div)
{
CRM->misc1_bit.clkoutdiv = clkout_div;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_debug.c
+98
View File
@@ -0,0 +1,98 @@
/**
**************************************************************************
* @file at32f421_debug.c
* @brief contains all the functions for the debug firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup DEBUG
* @brief DEBUG driver modules
* @{
*/
#ifdef DEBUG_MODULE_ENABLED
/** @defgroup DEBUG_private_functions
* @{
*/
/**
* @brief get debug device id
* @param none
* @retval the debug device id
*/
uint16_t debug_device_id_get(void)
{
return (uint16_t)DEBUGMCU->pid;
}
/**
* @brief set periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_SLEEP
* - DEBUG_DEEPSLEEP
* - DEBUG_STANDBY
* - DEBUG_WDT_PAUSE
* - DEBUG_WWDT_PAUSE
* - DEBUG_TMR1_PAUSE
* - DEBUG_TMR3_PAUSE
* - DEBUG_ERTC_PAUSE
* - DEBUG_I2C1_SMBUS_TIMEOUT
* - DEBUG_I2C2_SMBUS_TIMEOUT
* - DEBUG_TMR6_PAUSE
* - DEBUG_ERTC_512_PAUSE
* - DEBUG_TMR15_PAUSE
* - DEBUG_TMR16_PAUSE
* - DEBUG_TMR17_PAUSE
* - DEBUG_TMR14_PAUSE
* @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
DEBUGMCU->ctrl |= periph_debug_mode;
}
else
{
DEBUGMCU->ctrl &= ~periph_debug_mode;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_dma.c
+285
View File
@@ -0,0 +1,285 @@
/**
**************************************************************************
* @file at32f421_dma.c
* @brief contains all the functions for the dma firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
#ifdef DMA_MODULE_ENABLED
/** @defgroup DMA_private_functions
* @{
*/
/**
* @brief reset the dmax channely registers.
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @retval none
*/
void dma_reset(dma_channel_type* dmax_channely)
{
uint32_t temp = 0;
dmax_channely->ctrl_bit.chen = FALSE;
dmax_channely->ctrl = 0;
dmax_channely->dtcnt = 0;
dmax_channely->paddr = 0;
dmax_channely->maddr = 0;
temp = (uint32_t)dmax_channely;
/* dma1 channel */
DMA1->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
}
/**
* @brief set the number of data to be transferred
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param data_number: the number of data to be transferred(0x0000~0xFFFF)
* transfer.
* @retval none.
*/
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number)
{
dmax_channely->dtcnt = data_number;
}
/**
* @brief get number of data from dtcnt register
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @retval the number of data.
*/
uint16_t dma_data_number_get(dma_channel_type* dmax_channely)
{
return (uint16_t)dmax_channely->dtcnt;
}
/**
* @brief enable or disable dma interrupt
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param dma_int:
* this parameter can be any combination of the following values:
* - DMA_FDT_INT
* - DMA_HDT_INT
* - DMA_DTERR_INT
* @param new_state (TRUE or FALSE)
* @retval none
*/
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state)
{
if (new_state != FALSE)
{
dmax_channely->ctrl |= dma_int;
}
else
{
dmax_channely->ctrl &= ~dma_int;
}
}
/**
* @brief enable or disable dma channely
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param new_state (TRUE or FALSE)
* @retval None
*/
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state)
{
dmax_channely->ctrl_bit.chen = new_state;
}
/**
* @brief get dma interrupt flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval state of dma flag
*/
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
temp = DMA1->sts;
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval state of dma flag
*/
flag_status dma_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
temp = DMA1->sts;
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief clear dma flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* @retval none
*/
void dma_flag_clear(uint32_t dmax_flag)
{
DMA1->clr = dmax_flag;
}
/**
* @brief dma init config with its default value.
* @param dma_init_struct : pointer to a dma_init_type structure which will
* be initialized.
* @retval none
*/
void dma_default_para_init(dma_init_type* dma_init_struct)
{
dma_init_struct->peripheral_base_addr = 0x0;
dma_init_struct->memory_base_addr = 0x0;
dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct->buffer_size = 0x0;
dma_init_struct->peripheral_inc_enable = FALSE;
dma_init_struct->memory_inc_enable = FALSE;
dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct->loop_mode_enable = FALSE;
dma_init_struct->priority = DMA_PRIORITY_LOW;
}
/**
* @brief dma init
* @param dmax_channely:
* this parameter can be one of the following values:
* - DMA1_CHANNEL1
* - DMA1_CHANNEL2
* - DMA1_CHANNEL3
* - DMA1_CHANNEL4
* - DMA1_CHANNEL5
* @param dma_initstruct : pointer to a dma_init_type structure.
* @retval none
*/
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct)
{
/* clear ctrl register dtd bit and m2m bit */
dmax_channely->ctrl &= 0xbfef;
dmax_channely->ctrl |= dma_init_struct->direction;
dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
dmax_channely->dtcnt = dma_init_struct->buffer_size;
dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
dmax_channely->maddr = dma_init_struct->memory_base_addr;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_ertc.c
+1332
View File
File diff suppressed because it is too large Load Diff
DLD960LoopBootloader/libraries/drivers/src/at32f421_exint.c
+254
View File
@@ -0,0 +1,254 @@
/**
**************************************************************************
* @file at32f421_exint.c
* @brief contains all the functions for the exint firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup EXINT
* @brief EXINT driver modules
* @{
*/
#ifdef EXINT_MODULE_ENABLED
/** @defgroup EXINT_private_functions
* @{
*/
/**
* @brief exint reset
* @param none
* @retval none
*/
void exint_reset(void)
{
EXINT->inten = 0x00000000;
EXINT->polcfg1 = 0x00000000;
EXINT->polcfg2 = 0x00000000;
EXINT->evten = 0x00000000;
EXINT->intsts = 0x003FFFFF;
}
/**
* @brief exint default para init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_default_para_init(exint_init_type *exint_struct)
{
exint_struct->line_enable = FALSE;
exint_struct->line_select = EXINT_LINE_NONE;
exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
exint_struct->line_mode = EXINT_LINE_EVENT;
}
/**
* @brief exint init
* @param exint_struct
* - to the structure of exint_init_type
* @retval none
*/
void exint_init(exint_init_type *exint_struct)
{
uint32_t line_index = 0;
line_index = exint_struct->line_select;
EXINT->inten &= ~line_index;
EXINT->evten &= ~line_index;
if(exint_struct->line_enable != FALSE)
{
if(exint_struct->line_mode == EXINT_LINE_INTERRUPT)
{
EXINT->inten |= line_index;
}
else
{
EXINT->evten |= line_index;
}
EXINT->polcfg1 &= ~line_index;
EXINT->polcfg2 &= ~line_index;
if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
{
EXINT->polcfg1 |= line_index;
}
else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
{
EXINT->polcfg2 |= line_index;
}
else
{
EXINT->polcfg1 |= line_index;
EXINT->polcfg2 |= line_index;
}
}
}
/**
* @brief clear exint flag
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval none
*/
void exint_flag_clear(uint32_t exint_line)
{
EXINT->intsts = exint_line;
}
/**
* @brief get exint flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval state of exint flag
*/
flag_status exint_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get exint interrupt flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval state of exint flag
*/
flag_status exint_interrupt_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag =0;
exint_flag = EXINT->intsts & exint_line;
exint_flag = exint_flag & EXINT->inten;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief generate exint software interrupt event
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @retval none
*/
void exint_software_interrupt_event_generate(uint32_t exint_line)
{
EXINT->swtrg |= exint_line;
}
/**
* @brief enable or disable exint interrupt
* @param exint_line
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @param new_state (TRUE or FALSE)
* @retval none
*/
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->inten |= exint_line;
}
else
{
EXINT->inten &= ~exint_line;
}
}
/**
* @brief enable or disable exint event
* this parameter can be any combination of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* @param new_state (TRUE or FALSE)
* @retval none
*/
void exint_event_enable(uint32_t exint_line, confirm_state new_state)
{
if(new_state == TRUE)
{
EXINT->evten |= exint_line;
}
else
{
EXINT->evten &= ~exint_line;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_flash.c
+851
View File
@@ -0,0 +1,851 @@
/**
**************************************************************************
* @file at32f421_flash.c
* @brief contains all the functions for the flash firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup FLASH
* @brief FLASH driver modules
* @{
*/
#ifdef FLASH_MODULE_ENABLED
/** @defgroup FLASH_private_functions
* @{
*/
/**
* @brief check whether the specified flash flag is set or not.
* @param flash_flag: specifies the flash flag to check.
* this parameter can be one of flash flag status:
* - FLASH_OBF_FLAG
* - FLASH_ODF_FLAG
* - FLASH_PRGMERR_FLAG
* - FLASH_EPPERR_FLAG
* - FLASH_USDERR_FLAG
* @retval the new state of flash_flag (SET or RESET).
*/
flag_status flash_flag_get(uint32_t flash_flag)
{
flag_status status = RESET;
uint32_t flag_position;
flag_position = flash_flag & 0x70000000;
flash_flag &= 0x8FFFFFFF;
switch(flag_position)
{
case 0x00000000:
if(FLASH->sts & flash_flag)
status = SET;
break;
case 0x40000000:
if(FLASH->usd & flash_flag)
status = SET;
break;
default:
break;
}
/* return the new state of flash_flag (SET or RESET) */
return status;
}
/**
* @brief clear the flash flag.
* @param flash_flag: specifies the flash flags to clear.
* this parameter can be any combination of the following values:
* - FLASH_ODF_FLAG
* - FLASH_PRGMERR_FLAG
* - FLASH_EPPERR_FLAG
* @retval none
*/
void flash_flag_clear(uint32_t flash_flag)
{
FLASH->sts = flash_flag;
}
/**
* @brief return the flash operation status.
* @param none
* @retval status: the returned value can be: FLASH_OPERATE_BUSY,
* FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
*/
flash_status_type flash_operation_status_get(void)
{
flash_status_type flash_status = FLASH_OPERATE_DONE;
if(FLASH->sts_bit.obf != RESET)
{
flash_status = FLASH_OPERATE_BUSY;
}
else if(FLASH->sts_bit.prgmerr != RESET)
{
flash_status = FLASH_PROGRAM_ERROR;
}
else if(FLASH->sts_bit.epperr != RESET)
{
flash_status = FLASH_EPP_ERROR;
}
else
{
flash_status = FLASH_OPERATE_DONE;
}
/* return the flash status */
return flash_status;
}
/**
* @brief wait for flash operation complete or timeout.
* @param time_out: flash operation timeout
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_operation_wait_for(uint32_t time_out)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* check for the flash status */
status = flash_operation_status_get();
while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
{
status = flash_operation_status_get();
time_out--;
}
if(time_out == 0x00)
{
status = FLASH_OPERATE_TIMEOUT;
}
/* return the status */
return status;
}
/**
* @brief unlock the flash controller.
* @param none
* @retval none
*/
void flash_unlock(void)
{
FLASH->unlock = FLASH_UNLOCK_KEY1;
FLASH->unlock = FLASH_UNLOCK_KEY2;
}
/**
* @brief lock the flash controller.
* @param none
* @retval none
*/
void flash_lock(void)
{
FLASH->ctrl_bit.oplk = TRUE;
}
/**
* @brief erase a specified flash sector.
* @param sector_address: the sector address to be erased.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_sector_erase(uint32_t sector_address)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.secers = TRUE;
FLASH->addr = sector_address;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the secers bit */
FLASH->ctrl_bit.secers = FALSE;
/* return the erase status */
return status;
}
/**
* @brief erase flash all internal sectors.
* @param none
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_internal_all_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.bankers = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the bankers bit */
FLASH->ctrl_bit.bankers = FALSE;
/* return the erase status */
return status;
}
/**
* @brief erase the flash user system data.
* @note this functions erases all user system data except the fap byte.
* when fap high level enabled, can't use this function.
* @param none
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_user_system_data_erase(void)
{
flash_status_type status = FLASH_OPERATE_DONE;
uint16_t fap_val = FAP_RELIEVE_KEY;
/* get the flash access protection status */
if(flash_fap_status_get() != RESET)
{
fap_val = 0x0000;
}
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* erase the user system data */
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
/* restore the last flash access protection value */
USD->fap = (uint16_t)fap_val;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/*disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
/* return the erase status */
return status;
}
/**
* @brief program a word at a specified address.
* @param address: specifies the address to be programmed, word alignment is recommended.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_word_program(uint32_t address, uint32_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint32_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a halfword at a specified address.
* @param address: specifies the address to be programmed, halfword alignment is recommended.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a byte at a specified address.
* @param address: specifies the address to be programmed.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_byte_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
FLASH->ctrl_bit.fprgm = TRUE;
*(__IO uint8_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
/* return the program status */
return status;
}
/**
* @brief program a halfword at a specified user system data address.
* @param address: specifies the address to be programmed.
* @param data: specifies the data to be programmed.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
*(__IO uint16_t*)address = data;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the user system data program status */
return status;
}
/**
* @brief config erase/program protection for the desired sectors.
* @param sector_bits(1:ENABLE, 0:DISABLE)
* the pointer of the address of the sectors to be erase/program protected.
* the first 16bits general every bit is used to protect the 4KB bytes. the
* bit 31 is used to protect the extension memory.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_epp_set(uint32_t *sector_bits)
{
uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
flash_status_type status = FLASH_OPERATE_DONE;
sector_bits[0] = (uint32_t)(~sector_bits[0]);
epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usdprgm = TRUE;
USD->epp0 = epp_data[0];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
USD->epp1 = epp_data[1];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp2 = epp_data[2];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
if(status == FLASH_OPERATE_DONE)
{
USD->epp3 = epp_data[3];
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the erase/program protection operation status */
return status;
}
/**
* @brief return the flash erase/program protection status.
* @param sector_bits: pointer to get the epps register.
* @retval none
*/
void flash_epp_status_get(uint32_t *sector_bits)
{
/* return the flash erase/program protection register value */
sector_bits[0] = (uint32_t)(FLASH->epps);
}
/**
* @brief enable or disable the flash access protection.
* @note if the user has already programmed the other user system data before calling
* this function, must re-program them since this function erase all user system data.
* @param new_state: new state of the flash access protection.
* this parameter can be: TRUE or FALSE.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_fap_enable(confirm_state new_state)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
if(new_state == FALSE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_RELIEVE_KEY;
/* Wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
/* return the flash access protection operation status */
return status;
}
/**
* @brief check the flash access protection status.
* @param none
* @retval flash access protection status(SET or RESET)
*/
flag_status flash_fap_status_get(void)
{
return (flag_status)FLASH->usd_bit.fap;
}
/**
* @brief enable or disable the flash access protection high level.
* @note if the user has already programmed the other user system data before calling
* this function, must re-program them since this function erase all user system data.
* @param new_state: new state of the flash access protection high level.
* this parameter can be: TRUE or FALSE.
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_fap_high_level_enable(confirm_state new_state)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
if(new_state == FALSE)
{
FLASH->ctrl_bit.fap_hl_dis = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_RELIEVE_KEY;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
else
{
FLASH->ctrl_bit.usders = TRUE;
FLASH->ctrl_bit.erstr = TRUE;
/* wait for operation to be completed */
status = flash_operation_wait_for(ERASE_TIMEOUT);
/* disable the usders bit */
FLASH->ctrl_bit.usders = FALSE;
if(status == FLASH_OPERATE_DONE)
{
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->fap = FAP_HIGH_LEVEL_KEY;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
}
}
/* return the flash access protection operation status */
return status;
}
/**
* @brief check the flash access protection high level status.
* @param none
* @retval flash access protection high level status(SET or RESET)
*/
flag_status flash_fap_high_level_status_get(void)
{
return (flag_status)FLASH->usd_bit.fap_hl;
}
/**
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1.
* @param usd_ssb: the system setting byte
* @note this parameter usd_ssb must contain a combination of all the following 4 types of data
* type 1: wdt_ato_en, select the wdt auto start
* this data can be one of the following values:
* - USD_WDT_ATO_DISABLE: disable wdt auto start
* - USD_WDT_ATO_ENABLE: enable wdt auto start
* type 2: depslp_rst, reset event when entering deepsleep mode.
* this data can be one of the following values:
* - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
* - USD_DEPSLP_RST: reset generated when entering in deepsleep
* type 3: stdby_rst, reset event when entering standby mode.
* this data can be one of the following values:
* - USD_STDBY_NO_RST: no reset generated when entering in standby
* - USD_STDBY_RST: reset generated when entering in standby
* type 4: boot1, at startup, when boot0 pin is high level, selected the device boot from bootmem/sram.
* this data can be one of the following values:
* - USD_BOOT1_LOW: when boot0 is high level, boot from bootmem
* - USD_BOOT1_HIGH: when boot0 is high level, boot from sram
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_ssb_set(uint8_t usd_ssb)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock the user system data */
FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
while(FLASH->ctrl_bit.usdulks==RESET);
/* enable the user system data programming operation */
FLASH->ctrl_bit.usdprgm = TRUE;
USD->ssb = usd_ssb;
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
/* disable the usdprgm bit */
FLASH->ctrl_bit.usdprgm = FALSE;
/* return the user system data program status */
return status;
}
/**
* @brief return the flash system setting byte status.
* @param none
* @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
* stdby_rst(bit2) and boot1(bit4).
*/
uint8_t flash_ssb_status_get(void)
{
/* return the system setting byte status */
return (uint8_t)(FLASH->usd >> 2);
}
/**
* @brief enable or disable the specified flash interrupts.
* @param flash_int: specifies the flash interrupt sources to be enabled or disabled.
* this parameter can be any combination of the following values:
* - FLASH_ERR_INT
* - FLASH_ODF_INT
* @param new_state: new state of the specified flash interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
{
if(flash_int & FLASH_ERR_INT)
FLASH->ctrl_bit.errie = new_state;
if(flash_int & FLASH_ODF_INT)
FLASH->ctrl_bit.odfie = new_state;
}
/**
* @brief enable main block security library function.
* @param pwd: slib password
* start_sector: security library start sector
* inst_start_sector: security library i-bus area start sector
* end_sector: security library end sector
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector)
{
uint32_t slib_range;
flash_status_type status = FLASH_OPERATE_DONE;
/*check range param limits*/
if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \
(inst_start_sector != 0x7FF)) || (start_sector > end_sector))
return FLASH_PROGRAM_ERROR;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
slib_range = ((uint32_t)(inst_start_sector << 11) & FLASH_SLIB_INST_START_SECTOR) | \
((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \
(start_sector & FLASH_SLIB_START_SECTOR);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->slib_set_range = slib_range;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
return status;
}
/**
* @brief disable main block slib when slib enabled.
* @param pwd: slib password
* @retval success or error
*/
error_status flash_slib_disable(uint32_t pwd)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* write password to disable slib */
FLASH->slib_pwd_clr = pwd;
status = flash_operation_wait_for(ERASE_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
return SUCCESS;
else
return ERROR;
}
return ERROR;
}
/**
* @brief get the main block slib state.
* @param none
* @retval SET or RESET
*/
flag_status flash_slib_state_get(void)
{
if(FLASH->slib_sts0_bit.slib_enf)
return SET;
else
return RESET;
}
/**
* @brief get the main block start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_start_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
}
/**
* @brief get the main block inst start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_inststart_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_inst_ss;
}
/**
* @brief get the main block end sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_slib_end_sector_get(void)
{
return (uint16_t)FLASH->slib_sts1_bit.slib_es;
}
/**
* @brief flash crc calibration.
* @param start_addr: crc calibration start sector address
* sector_cnt: crc calibration sector count
* @retval uint32: crc calibration result
*/
uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt)
{
FLASH->crc_addr = start_addr;
FLASH->crc_ctrl = sector_cnt | 0x10000;
flash_operation_wait_for(OPERATION_TIMEOUT);
return FLASH->crc_chkr;
}
/**
* @brief enable boot memory as extension mode.
* @note this function is irreversible, can not disable!!!
* @param none
* @retval none.
*/
void flash_boot_memory_extension_mode_enable(void)
{
if(FLASH->slib_sts0_bit.btm_ap_enf == RESET)
{
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
FLASH->btm_mode_set = 0;
flash_operation_wait_for(OPERATION_TIMEOUT);
}
}
/**
* @brief enable extension memory security library function.
* @param pwd: slib password
* inst_start_sector: extension memory security library i-bus area start sector, range 0~3 or 0xFF
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t inst_start_sector)
{
flash_status_type status = FLASH_OPERATE_DONE;
/* unlock slib cfg register */
FLASH->slib_unlock = SLIB_UNLOCK_KEY;
while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
/* configure slib, set pwd and range */
FLASH->slib_set_pwd = pwd;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status == FLASH_OPERATE_DONE)
{
FLASH->em_slib_set = (uint32_t)(inst_start_sector << 16) + (uint32_t)0x5AA5;
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
}
return status;
}
/**
* @brief get the extension memory slib state.
* @param none
* @retval SET or RESET
*/
flag_status flash_extension_memory_slib_state_get(void)
{
if(FLASH->slib_sts0_bit.em_slib_enf)
return SET;
else
return RESET;
}
/**
* @brief get the extension memory inst start sector of slib.
* @param none
* @retval uint16_t
*/
uint16_t flash_em_slib_inststart_sector_get(void)
{
return (uint16_t)FLASH->slib_sts0_bit.em_slib_inst_ss;
}
/**
* @brief config flash low power mode enable or disable.
* if enabled, when system entry deep sleep mode, flash also entry low power mode.
* @param new_state: new state of the flash low power mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void flash_low_power_mode_enable(confirm_state new_state)
{
FLASH->ctrl_bit.lpmen = new_state;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_gpio.c
+493
View File
@@ -0,0 +1,493 @@
/**
**************************************************************************
* @file at32f421_gpio.c
* @brief contains all the functions for the gpio firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
#ifdef GPIO_MODULE_ENABLED
/** @defgroup GPIO_private_functions
* @{
*/
/**
* @brief reset the gpio register
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval none
*/
void gpio_reset(gpio_type *gpio_x)
{
if(gpio_x == GPIOA)
{
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOB)
{
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOC)
{
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
}
else if(gpio_x == GPIOF)
{
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the gpio peripheral.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_init_struct: pointer to gpio init structure.
* @retval none
*/
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
{
uint16_t pinx_value, pin_index = 0;
pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
while(pinx_value > 0)
{
if(pinx_value & 0x01)
{
gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
}
pinx_value >>= 1;
pin_index++;
}
}
/**
* @brief fill each gpio_init_type member with its default value.
* @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
* @retval none
*/
void gpio_default_para_init(gpio_init_type *gpio_init_struct)
{
/* reset gpio init structure parameters values */
gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
}
/**
* @brief read the specified input port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if(pins != (pins & gpio_x->idt))
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief read the specified gpio input data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
uint16_t gpio_input_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->idt));
}
/**
* @brief read the specified output port pin.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* @retval flag_status (SET or RESET)
*/
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
{
flag_status status = RESET;
if((gpio_x->odt & pins) != RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief read the specified gpio ouput data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
uint16_t gpio_output_data_read(gpio_type *gpio_x)
{
return ((uint16_t)(gpio_x->odt));
}
/**
* @brief set the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->scr = pins;
}
/**
* @brief clear the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
{
gpio_x->clr = pins;
}
/**
* @brief set or clear the selected data port bit.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
* @retval none
*/
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
{
if(bit_state != FALSE)
{
gpio_x->scr = pins;
}
else
{
gpio_x->clr = pins;
}
}
/**
* @brief write data to the specified gpio data port.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param port_value: specifies the value to be written to the port output data register.
* @retval none
*/
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
{
gpio_x->odt = port_value;
}
/**
* @brief write protect gpio pins configuration registers.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be any combination of the following:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @retval none
*/
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
{
uint32_t temp = 0x00010000;
temp |= pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* reset wpen bit */
gpio_x->wpr = pins;
/* set wpen bit */
gpio_x->wpr = temp;
/* read wpen bit*/
temp = gpio_x->wpr;
/* read wpen bit*/
temp = gpio_x->wpr;
}
/**
* @brief enable or disable gpio pins huge driven.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
* - GPIO_PINS_3
* - GPIO_PINS_4
* - GPIO_PINS_5
* - GPIO_PINS_6
* - GPIO_PINS_7
* - GPIO_PINS_8
* - GPIO_PINS_9
* - GPIO_PINS_10
* - GPIO_PINS_11
* - GPIO_PINS_12
* - GPIO_PINS_13
* - GPIO_PINS_14
* - GPIO_PINS_15
* - GPIO_PINS_ALL
* @param new_state: new state of the slew rate.
* this parameter can be: true or false.
* @retval none
*/
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
{
if(new_state != FALSE)
{
gpio_x->hdrv |= pins;
}
else
{
gpio_x->hdrv &= ~pins;
}
}
/**
* @brief configure the pin's muxing function.
* @param gpio_x: to select the gpio peripheral.
* this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_pin_source: specifies the pin for the muxing function.
* this parameter can be one of the following values:
* - GPIO_PINS_SOURCE0
* - GPIO_PINS_SOURCE1
* - GPIO_PINS_SOURCE2
* - GPIO_PINS_SOURCE3
* - GPIO_PINS_SOURCE4
* - GPIO_PINS_SOURCE5
* - GPIO_PINS_SOURCE6
* - GPIO_PINS_SOURCE7
* - GPIO_PINS_SOURCE8
* - GPIO_PINS_SOURCE9
* - GPIO_PINS_SOURCE10
* - GPIO_PINS_SOURCE11
* - GPIO_PINS_SOURCE12
* - GPIO_PINS_SOURCE13
* - GPIO_PINS_SOURCE14
* - GPIO_PINS_SOURCE15
* @param gpio_mux: select the pin to used as muxing function.
* this parameter can be one of the following values:
* - GPIO_MUX_0
* - GPIO_MUX_1
* - GPIO_MUX_2
* - GPIO_MUX_3
* - GPIO_MUX_4
* - GPIO_MUX_5
* - GPIO_MUX_6
* - GPIO_MUX_7
* @retval none
*/
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
if(gpio_pin_source >> 0x03)
{
gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxh | temp;
gpio_x->muxh = temp_2;
}
else
{
gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
temp_2 = gpio_x->muxl | temp;
gpio_x->muxl = temp_2;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_i2c.c
+730
View File
@@ -0,0 +1,730 @@
/**
**************************************************************************
* @file at32f421_i2c.c
* @brief contains all the functions for the i2c firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup I2C
* @brief I2C driver modules
* @{
*/
#ifdef I2C_MODULE_ENABLED
/** @defgroup I2C_private_functions
* @{
*/
/**
* @brief reset the i2c register
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none
*/
void i2c_reset(i2c_type *i2c_x)
{
if(i2c_x == I2C1)
{
crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
}
else if(i2c_x == I2C2)
{
crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
}
}
/**
* @brief software reset.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.reset = new_state;
}
/**
* @brief init i2c speed and duty cycle.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param duty
* this parameter can be one of the following values:
* - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
* - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
* @param speed: i2c scl clock speed, such as 100000
* @retval none
*/
void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed)
{
uint32_t apb_freq = 0;
uint16_t freq_mhz = 0, temp = 0;
crm_clocks_freq_type clocks;
/* disable i2c peripherals */
i2c_x->ctrl1_bit.i2cen = FALSE;
/* get system clock */
crm_clocks_freq_get(&clocks);
if((i2c_x == I2C1) || (i2c_x == I2C2))
{
apb_freq = clocks.apb1_freq;
}
freq_mhz = (apb_freq / 1000000);
/* set i2c input clock frequency */
i2c_x->ctrl2_bit.clkfreq = freq_mhz;
/* standard mode */
if(speed <= 100000)
{
temp = (uint16_t)(apb_freq / (speed << 1));
if (temp < 0x04)
{
temp = 0x04;
}
/* set scl clock */
i2c_x->clkctrl_bit.speed = temp;
/* disable fast mode */
i2c_x->clkctrl_bit.speedmode = FALSE;
/* set the maximum rise time */
if((freq_mhz + 1) > 0x3F)
{
i2c_x->tmrise_bit.risetime = 0x3F;
}
else
{
i2c_x->tmrise_bit.risetime = (freq_mhz + 1);
}
}
/* fast mode */
else
{
if (duty == I2C_FSMODE_DUTY_2_1)
{
temp = (uint16_t)(apb_freq / (speed * 3));
/* the ratio of high level to low level is 1:2 */
i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_2_1;
}
else
{
temp = (uint16_t)(apb_freq / (speed * 25));
/* the ratio of high level to low level is 9:16 */
i2c_x->clkctrl_bit.dutymode = I2C_FSMODE_DUTY_16_9;
}
if (temp == 0)
{
temp = 0x0001;
}
/* set scl clock*/
i2c_x->clkctrl_bit.speed = temp;
/* set the mode to fast mode */
i2c_x->clkctrl_bit.speedmode = TRUE;
/* set the maximum rise time */
if(speed <= 400000)
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
else
{
i2c_x->tmrise_bit.risetime = (uint16_t)(((freq_mhz * (uint16_t)120) / (uint16_t)1000) + (uint16_t)1);
}
}
}
/**
* @brief config own address1.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param mode
* this parameter can be one of the following values:
* - I2C_ADDRESS_MODE_7BIT: 7bit address.
* - I2C_ADDRESS_MODE_10BIT: 10bit address.
* @param address: own address1, such as 0xb0.
* @retval none
*/
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
{
/* set address mode */
i2c_x->oaddr1_bit.addr1mode = mode;
/* set own address1 */
i2c_x->oaddr1_bit.addr1 = address;
}
/**
* @brief config own address2.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: specifies the 7bit i2c own address2, such as 0xa0.
* @retval none.
*/
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address)
{
i2c_x->oaddr2_bit.addr2 = (address >> 1);
}
/**
* @brief enable or disable own address2.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->oaddr2_bit.addr2en = new_state;
}
/**
* @brief enable or disable the smbus mode
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.permode = new_state;
}
/**
* @brief enable or disable i2c periph
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.i2cen = new_state;
}
/**
* @brief config fast mode duty cycle
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param duty
* this parameter can be one of the following values:
* - I2C_FSMODE_DUTY_2_1: duty cycle 2:1
* - I2C_FSMODE_DUTY_16_9: duty cycle 16:9
* @retval none
*/
void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty)
{
i2c_x->clkctrl_bit.dutymode = duty;
}
/**
* @brief enable or disable clock stretch.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.stretch = !new_state;
}
/**
* @brief enable or disable acknowledge.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none.
*/
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.acken = new_state;
}
/**
* @brief master receiving mode acknowledge control.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param pos
* this parameter can be one of the following values:
* - I2C_MASTER_ACK_CURRENT: acken bit acts on the current byte
* - I2C_MASTER_ACK_NEXT: acken bit acts on the next byte
* @retval none
*/
void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos)
{
i2c_x->ctrl1_bit.mackctrl = pos;
}
/**
* @brief pec position set.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param pos
* this parameter can be one of the following values:
* - I2C_PEC_POSITION_CURRENT: the current byte is pec
* - I2C_PEC_POSITION_NEXT: the next byte is pec
* @retval none
*/
void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos)
{
i2c_x->ctrl1_bit.mackctrl = pos;
}
/**
* @brief enable or disable general call.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.gcaen = new_state;
}
/**
* @brief enable or disable arp mode.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.arpen = new_state;
}
/**
* @brief config smbus host or device.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
* this parameter can be one of the following values:
* - I2C_SMBUS_MODE_DEVICE: smbus device.
* - I2C_SMBUS_MODE_HOST: smbus host.
* @retval none
*/
void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode)
{
i2c_x->ctrl1_bit.smbmode = mode;
}
/**
* @brief drive the smbus alert pin high or low.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
* this parameter can be one of the following values:
* - I2C_SMBUS_ALERT_LOW: smbus alert pin set low.
* - I2C_SMBUS_ALERT_HIGH: smbus alert pin set high.
* @retval none
*/
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
{
i2c_x->ctrl1_bit.smbalert = level;
}
/**
* @brief enable or disable pec transfer.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.pecten = new_state;
}
/**
* @brief enable or disable pec calcultetion.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl1_bit.pecen = new_state;
}
/**
* @brief get pec value.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval uint8_t: pec value.
*/
uint8_t i2c_pec_value_get(i2c_type *i2c_x)
{
return i2c_x->sts2_bit.pecval;
}
/**
* @brief enable or disable if the next dma transfer will be the last one.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.dmaend = new_state;
}
/**
* @brief enable or disable dma requests.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state)
{
i2c_x->ctrl2_bit.dmaen = new_state;
}
/**
* @brief enable or disable interrupt
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param source
* this parameter can be one of the following values:
* - I2C_DATA_INT: data interrupt.
* - I2C_EV_INT: event interrupt.
* - I2C_ERR_INT: error interrupt.
* @param new_state (TRUE or FALSE)
* @retval none
*/
void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state)
{
if (new_state != FALSE)
{
i2c_x->ctrl2 |= source;
}
else
{
i2c_x->ctrl2 &= (uint16_t)~source;
}
}
/**
* @brief generate start condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none.
*/
void i2c_start_generate(i2c_type *i2c_x)
{
i2c_x->ctrl1_bit.genstart = TRUE;
}
/**
* @brief generate stop condition.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none.
*/
void i2c_stop_generate(i2c_type *i2c_x)
{
i2c_x->ctrl1_bit.genstop = TRUE;
}
/**
* @brief transmit the slave address.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: specifies the slave address which will be transmitted
* @param direction
* this parameter can be one of the following values:
* - I2C_DIRECTION_TRANSMIT: transmit mode.
* - I2C_DIRECTION_RECEIVE: receive mode.
* @retval none.
*/
void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction)
{
if(direction == I2C_DIRECTION_TRANSMIT)
{
i2c_x->dt = address & 0xFE;
}
else
{
i2c_x->dt = address | 0x01;
}
}
/**
* @brief send a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param data: byte to be transmitted.
* @retval none
*/
void i2c_data_send(i2c_type *i2c_x, uint8_t data)
{
i2c_x->dt = data;
}
/**
* @brief receive a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @retval uint8_t: received byte
*/
uint8_t i2c_data_receive(i2c_type *i2c_x)
{
return (uint8_t)i2c_x->dt;
}
/**
* @brief get flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param flag
* this parameter can be one of the following values:
* - I2C_STARTF_FLAG: start condition generation complete flag.
* - I2C_ADDR7F_FLAG: 0~7 bit address match flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_TRMODE_FLAG: transmission mode.
* - I2C_BUSYF_FLAG: bus busy flag transmission mode.
* - I2C_DIRF_FLAG: transmission direction flag.
* - I2C_GCADDRF_FLAG: general call address received flag.
* - I2C_DEVADDRF_FLAG: smbus device address received flag.
* - I2C_HOSTADDRF_FLAG: smbus host address received flag.
* - I2C_ADDR2_FLAG: own address 2 received flag.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t reg = 0, value = 0;
reg = flag >> 28;
flag &= (uint32_t)0x00FFFFFF;
if(reg == 0)
{
value = i2c_x->sts1;
}
else
{
flag = (uint32_t)(flag >> 16);
value = i2c_x->sts2;
}
if((value & flag) != (uint32_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief get interrupt flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2.
* @param flag
* this parameter can be one of the following values:
* - I2C_STARTF_FLAG: start condition generation complete flag.
* - I2C_ADDR7F_FLAG: 0~7 bit address match flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t reg = 0, value = 0, iten = 0;
switch(flag)
{
case I2C_STARTF_FLAG:
case I2C_ADDR7F_FLAG:
case I2C_TDC_FLAG:
case I2C_ADDRHF_FLAG:
case I2C_STOPF_FLAG:
iten = i2c_x->ctrl2_bit.evtien;
break;
case I2C_RDBF_FLAG:
case I2C_TDBE_FLAG:
iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien;
break;
case I2C_BUSERR_FLAG:
case I2C_ARLOST_FLAG:
case I2C_ACKFAIL_FLAG:
case I2C_OUF_FLAG:
case I2C_PECERR_FLAG:
case I2C_TMOUT_FLAG:
case I2C_ALERTF_FLAG:
iten = i2c_x->ctrl2_bit.errien;
break;
default:
break;
}
reg = flag >> 28;
flag &= (uint32_t)0x00FFFFFF;
if(reg == 0)
{
value = i2c_x->sts1;
}
else
{
flag = (uint32_t)(flag >> 16);
value = i2c_x->sts2;
}
if(((value & flag) != (uint32_t)RESET) && (iten))
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear flag status
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param flag
* this parameter can be any combination of the following values:
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag.
* @retval none
*/
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
{
i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00);
if(flag & I2C_ADDR7F_FLAG)
{
UNUSED(i2c_x->sts1);
UNUSED(i2c_x->sts2);
}
if(flag & I2C_STOPF_FLAG)
{
UNUSED(i2c_x->sts1);
i2c_x->ctrl1_bit.i2cen = TRUE;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_misc.c
+171
View File
@@ -0,0 +1,171 @@
/**
**************************************************************************
* @file at32f421_misc.c
* @brief contains all the functions for the misc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
#ifdef MISC_MODULE_ENABLED
/** @defgroup MISC_private_functions
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @brief system reset
* @param none
* @retval none
*/
void nvic_system_reset(void)
{
NVIC_SystemReset();
}
/**
* @brief enable nvic irq
* @param irqn (IRQn_Type number)
* @param preempt_priority: preemptive priority value (starting from 0)
* @param sub_priority: subpriority value (starting from 0)
* @retval none
*/
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
{
uint32_t temp_priority = 0;
/* encode priority */
temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
/* set priority */
NVIC_SetPriority(irqn, temp_priority);
/* enable irqn */
NVIC_EnableIRQ(irqn);
}
/**
* @brief disable nvic irq number
* @param irqn (IRQn_Type number)
* @retval none
*/
void nvic_irq_disable(IRQn_Type irqn)
{
NVIC_DisableIRQ(irqn);
}
/**
* @brief config nvic priority group
* @param priority_group
* this parameter can be one of the following values:
* - NVIC_PRIORITY_GROUP_0
* - NVIC_PRIORITY_GROUP_1
* - NVIC_PRIORITY_GROUP_2
* - NVIC_PRIORITY_GROUP_3
* - NVIC_PRIORITY_GROUP_4
* @retval none
*/
void nvic_priority_group_config(nvic_priority_group_type priority_group)
{
/* set the prigroup[10:8] bits according to nvic_prioritygroup value */
NVIC_SetPriorityGrouping(priority_group);
}
/**
* @brief set the vector table location and offset.
* @param base
* this parameter can be one of the following values:
* - NVIC_VECTTAB_RAM
* - NVIC_VECTTAB_FLASH
* @param offset (vector table base offset field. this value must be a multiple of 0x200)
* @retval none
*/
void nvic_vector_table_set(uint32_t base, uint32_t offset)
{
SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief config nvic lowpower mode
* @param lp_mode
* this parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
* @param new_state (new state of lp condition. ENABLE or DISABLE)
* @retval none
*/
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
SCB->SCR |= lp_mode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
}
}
/**
* @brief config systick clock source
* @param source
* this parameter can be one of the following values:
* - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
* - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
* @retval none
*/
void systick_clock_source_config(systick_clock_source_type source)
{
if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
{
SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
else
{
SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_pwc.c
+260
View File
@@ -0,0 +1,260 @@
/**
**************************************************************************
* @file at32f421_pwc.c
* @brief contains all the functions for the pwc firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup PWC
* @brief PWC driver modules
* @{
*/
#ifdef PWC_MODULE_ENABLED
/** @defgroup PWC_private_functions
* @{
*/
/**
* @brief deinitialize the pwc peripheral registers to their default reset values.
* @param none
* @retval none
*/
void pwc_reset(void)
{
crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
}
/**
* @brief enable or disable access to the battery powered domain.
* @param new_state: new state of battery powered domain access.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_battery_powered_domain_access(confirm_state new_state)
{
PWC->ctrl_bit.bpwen = new_state;
}
/**
* @brief select the voltage threshold detected by the power voltage detector.
* @param pvm_voltage: select pwc pvm voltage
* this parameter can be one of the following values:
* - PWC_PVM_VOLTAGE_2V3
* - PWC_PVM_VOLTAGE_2V4
* - PWC_PVM_VOLTAGE_2V5
* - PWC_PVM_VOLTAGE_2V6
* - PWC_PVM_VOLTAGE_2V7
* - PWC_PVM_VOLTAGE_2V8
* - PWC_PVM_VOLTAGE_2V9
* @retval none
*/
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
{
PWC->ctrl_bit.pvmsel = pvm_voltage;
}
/**
* @brief enable or disable pwc power voltage monitor (pvm)
* @param new_state: new state of pvm.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void pwc_power_voltage_monitor_enable(confirm_state new_state)
{
PWC->ctrl_bit.pvmen = new_state;
}
/**
* @brief enable or disable pwc standby wakeup pin
* @param pin_num: choose the wakeup pin.
* this parameter can be be any combination of the following values:
* - PWC_WAKEUP_PIN_1
* - PWC_WAKEUP_PIN_2
* - PWC_WAKEUP_PIN_6
* - PWC_WAKEUP_PIN_7
* @param new_state: new state of the standby wakeup pin.
* this parameter can be one of the following values:
* - TRUE <wakeup pin is used for wake up cpu from standby mode>
* - FALSE <wakeup pin is used for general purpose I/O>
* @retval none
*/
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
{
if(new_state == TRUE)
{
PWC->ctrlsts |= pin_num;
}
else
{
PWC->ctrlsts &= ~pin_num;
}
}
/**
* @brief clear flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be any combination of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
* @retval none
*/
void pwc_flag_clear(uint32_t pwc_flag)
{
if(pwc_flag & PWC_STANDBY_FLAG)
PWC->ctrl_bit.clsef = TRUE;
if(pwc_flag & PWC_WAKEUP_FLAG)
PWC->ctrl_bit.clswef = TRUE;
}
/**
* @brief get flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be one of the following values:
* - PWC_WAKEUP_FLAG
* - PWC_STANDBY_FLAG
* - PWC_PVM_OUTPUT_FLAG
* @retval state of select flag(SET or RESET).
*/
flag_status pwc_flag_get(uint32_t pwc_flag)
{
flag_status status = RESET;
if ((PWC->ctrlsts & pwc_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief enter pwc sleep mode
* @param sleep_mode_enter: choose the instruction to enter sleep mode.
* this parameter can be one of the following values:
* - PWC_SLEEP_ENTER_WFI
* - PWC_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
{
SCB->SCR &= (uint32_t)~0x4;
if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
{
__WFI();
}
}
/**
* @brief enter pwc deep-sleep mode
* @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
* this parameter can be one of the following values:
* - PWC_DEEP_SLEEP_ENTER_WFI
* - PWC_DEEP_SLEEP_ENTER_WFE
* @retval none
*/
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
{
SCB->SCR |= 0x04;
if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
{
__SEV();
__WFE();
__WFE();
}
else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
{
__WFI();
}
SCB->SCR &= (uint32_t)~0x4;
}
/**
* @brief regulate low power consumption in the deep sleep mode
* @param pwc_regulator: set the regulator state.
* this parameter can be one of the following values:
* - PWC_REGULATOR_ON
* - PWC_REGULATOR_LOW_POWER
* @retval none
*/
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
{
switch(pwc_regulator)
{
case PWC_REGULATOR_ON:
PWC->ctrl_bit.vrsel = FALSE;
break;
case PWC_REGULATOR_LOW_POWER:
PWC->ctrl_bit.vrsel = TRUE;
break;
default:
break;
}
}
/**
* @brief enter pwc standby mode
* @param none
* @retval none
*/
void pwc_standby_mode_enter(void)
{
PWC->ctrl_bit.clswef = TRUE;
PWC->ctrl_bit.lpsel = TRUE;
SCB->SCR |= 0x04;
#if defined (__CC_ARM)
__force_stores();
#endif
while(1)
{
__WFI();
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_scfg.c
+235
View File
@@ -0,0 +1,235 @@
/**
**************************************************************************
* @file at32f421_scfg.c
* @brief contains all the functions for the system config firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup SCFG
* @brief SCFG driver modules
* @{
*/
#ifdef SCFG_MODULE_ENABLED
/** @defgroup SCFG_private_functions
* @{
*/
/**
* @brief scfg reset
* @param none
* @retval none
*/
void scfg_reset(void)
{
crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
}
/**
* @brief scfg infrared config
* @param source
* this parameter can be one of the following values:
* - SCFG_IR_SOURCE_TMR16
* @param polarity
* this parameter can be one of the following values:
* - SCFG_IR_POLARITY_NO_AFFECTE
* - SCFG_IR_POLARITY_REVERSE
* @retval none
*/
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
{
SCFG->cfg1_bit.ir_src_sel = source;
SCFG->cfg1_bit.ir_pol = polarity;
}
/**
* @brief scfg memory address mapping get
* @param none
* @retval return parameter can be one of the following values:
* - SCFG_MEM_MAP_MAIN_MEMORY
* - SCFG_MEM_MAP_BOOT_MEMORY
* - SCFG_MEM_MAP_INTERNAL_SRAM
*/
uint8_t scfg_mem_map_get(void)
{
return (uint8_t)SCFG->cfg1_bit.mem_map_sel ;
}
/**
* @brief scfg pa11/12 pin remap
* @param pin_remap
* this parameter can be one of the following values:
* - SCFG_PA11PA12_NO_REMAP
* - SCFG_PA11PA12_TO_PA9PA10
* @retval none
*/
void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap)
{
SCFG->cfg1_bit.pa11_12_rmp = pin_remap;
}
/**
* @brief scfg adc dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_ADC_TO_DMA_CHANNEL_1
* - SCFG_ADC_TO_DMA_CHANNEL_2
* @retval none
*/
void scfg_adc_dma_channel_remap(scfg_adc_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.adc_dma_rmp = dma_channel;
}
/**
* @brief scfg usart1 tx dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_USART1_TX_TO_DMA_CHANNEL_2
* - SCFG_USART1_TX_TO_DMA_CHANNEL_4
* @retval none
*/
void scfg_usart1_tx_dma_channel_remap(scfg_usart1_tx_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.usart1_tx_dma_rmp = dma_channel;
}
/**
* @brief scfg usart1 rx dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_USART1_RX_TO_DMA_CHANNEL_3
* - SCFG_USART1_RX_TO_DMA_CHANNEL_5
* @retval none
*/
void scfg_usart1_rx_dma_channel_remap(scfg_usart1_rx_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.usart1_rx_dma_rmp = dma_channel;
}
/**
* @brief scfg tmr16 dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_TMR16_TO_DMA_CHANNEL_3
* - SCFG_TMR16_TO_DMA_CHANNEL_4
* @retval none
*/
void scfg_tmr16_dma_channel_remap(scfg_tmr16_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.tmr16_dma_rmp = dma_channel;
}
/**
* @brief scfg tmr17 dma channel remap
* @param dma_channel
* this parameter can be one of the following values:
* - SCFG_TMR17_TO_DMA_CHANNEL_1
* - SCFG_TMR17_TO_DMA_CHANNEL_2
* @retval none
*/
void scfg_tmr17_dma_channel_remap(scfg_tmr17_dma_remap_type dma_channel)
{
SCFG->cfg1_bit.tmr17_dma_rmp = dma_channel;
}
/**
* @brief select the gpio pin used as exint line.
* @param port_source:
* select the gpio port to be used as source for exint lines.
* this parameter can be one of the following values:
* - SCFG_PORT_SOURCE_GPIOA
* - SCFG_PORT_SOURCE_GPIOB
* - SCFG_PORT_SOURCE_GPIOC
* - SCFG_PORT_SOURCE_GPIOF
* @param pin_source:
* specifies the exint line to be configured.
* this parameter can be one of the following values:
* - SCFG_PINS_SOURCE0
* - SCFG_PINS_SOURCE1
* - SCFG_PINS_SOURCE2
* - SCFG_PINS_SOURCE3
* - SCFG_PINS_SOURCE4
* - SCFG_PINS_SOURCE5
* - SCFG_PINS_SOURCE6
* - SCFG_PINS_SOURCE7
* - SCFG_PINS_SOURCE8
* - SCFG_PINS_SOURCE9
* - SCFG_PINS_SOURCE10
* - SCFG_PINS_SOURCE11
* - SCFG_PINS_SOURCE12
* - SCFG_PINS_SOURCE13
* - SCFG_PINS_SOURCE14
* - SCFG_PINS_SOURCE15
* @retval none
*/
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
switch (pin_source >> 0x02)
{
case 0:
SCFG->exintc1 &= ~tmp;
SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 1:
SCFG->exintc2 &= ~tmp;
SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 2:
SCFG->exintc3 &= ~tmp;
SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
case 3:
SCFG->exintc4 &= ~tmp;
SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
break;
default:
break;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_spi.c
+675
View File
@@ -0,0 +1,675 @@
/**
**************************************************************************
* @file at32f421_spi.c
* @brief contains all the functions for the spi firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
#ifdef SPI_MODULE_ENABLED
/** @defgroup SPI_private_functions
* @{
*/
/**
* @brief spi reset by crm reset register
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval none
*/
void spi_i2s_reset(spi_type *spi_x)
{
if(spi_x == SPI1)
{
crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
}
#if defined (AT32F421Cx) || defined (AT32F421Kx) || defined (AT32F421Gx)
else if(spi_x == SPI2)
{
crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
}
#endif
}
/**
* @brief spi init config with its default value.
* @param spi_init_struct : pointer to a spi_init_type structure which will
* be initialized.
* @retval none
*/
void spi_default_para_init(spi_init_type* spi_init_struct)
{
spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
}
/**
* @brief spi init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
* @retval none
*/
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
{
spi_x->i2sctrl_bit.i2smsel = FALSE;
if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
{
spi_x->ctrl1_bit.slben = FALSE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = TRUE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = FALSE;
spi_x->ctrl1_bit.ora = FALSE;
}
else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
{
spi_x->ctrl1_bit.slben = TRUE;
spi_x->ctrl1_bit.slbtd = TRUE;
spi_x->ctrl1_bit.ora = FALSE;
}
spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
{
spi_x->ctrl1_bit.swcsil = TRUE;
}
else
{
spi_x->ctrl1_bit.swcsil = FALSE;
}
spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
if(spi_init_struct->mclk_freq_division > SPI_MCLK_DIV_256)
{
spi_x->ctrl2_bit.mdiv_h = 1;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
}
else
{
spi_x->ctrl2_bit.mdiv_h = 0;
spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
}
spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
}
/**
* @brief spi next transmit crc for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval none
*/
void spi_crc_next_transmit(spi_type* spi_x)
{
spi_x->ctrl1_bit.ntc = TRUE;
}
/**
* @brief set the crc polynomial value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param crc_poly: crc polynomial value.
* @retval none
*/
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
{
spi_x->cpoly_bit.cpoly = crc_poly;
}
/**
* @brief return the crc polynomial register value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval the select crc polynomial register value
*/
uint16_t spi_crc_polynomial_get(spi_type* spi_x)
{
return spi_x->cpoly_bit.cpoly;
}
/**
* @brief enable or disable the hardware crc calculation for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of crc calculation.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.ccen = new_state;
}
/**
* @brief return the transmit or the receive crc value for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param crc_direction: select transmit or receive crc value to be read
* - SPI_CRC_RX
* - SPI_CRC_TX
* @retval the select crc register value
*/
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
{
if(crc_direction == SPI_CRC_RX)
return spi_x->rcrc_bit.rcrc;
else
return spi_x->tcrc_bit.tcrc;
}
/**
* @brief enable or disable the hardware cs output for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of spi master cs output.
* this parameter can be: TRUE or FALSE.
* note:the bit only use in spi master mode
* @retval none
*/
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.hwcsoe = new_state;
}
/**
* @brief set the software cs internal level for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param level: set the state of spi cs level.
* this parameter can be one of the following values:
* - SPI_SWCS_INTERNAL_LEVEL_LOW
* - SPI_SWCS_INTERNAL_LEVEL_HIGHT
* note:the bit only use when swcsen bit is set.
* note:when use this bit,io operation on the cs pin are invalid.
* @retval none
*/
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
{
spi_x->ctrl1_bit.swcsil = level;
}
/**
* @brief set the data frame bit num for the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param bit_num: set the data frame size
* - SPI_FRAME_8BIT
* - SPI_FRAME_16BIT
* @retval none
*/
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
{
spi_x->ctrl1_bit.fbn = bit_num;
}
/**
* @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param direction: data transfer direction
* this parameter can be one of the following values:
* - SPI_HALF_DUPLEX_DIRECTION_RX
* - SPI_HALF_DUPLEX_DIRECTION_TX
* @retval none
*/
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
{
spi_x->ctrl1_bit.slbtd = direction;
}
/**
* @brief enable or disable spi.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of spi.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl1_bit.spien = new_state;
}
/**
* @brief i2s init config with its default value.
* @param i2s_init_struct : pointer to a i2s_init_type structure which will
* be initialized.
* @retval none
*/
void i2s_default_para_init(i2s_init_type* i2s_init_struct)
{
i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
i2s_init_struct->mclk_output_enable = FALSE;
}
/**
* @brief i2s init config with its setting value.
* @param spi_x: select the spi peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
* @retval none
*/
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
{
crm_clocks_freq_type clocks_freq;
uint32_t i2s_sclk_index = 0;
uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
/* i2s audio frequency config */
if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
else
{
crm_clocks_freq_get(&clocks_freq);
i2s_sclk_index = clocks_freq.sclk_freq;
if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
else
{
if(i2s_init_struct->mclk_output_enable == TRUE)
{
frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
else
{
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
else
frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
}
}
}
frequency_index = frequency_index / 10;
i2sodd_index = frequency_index & (uint16_t)0x0001;
i2sdiv_index = (frequency_index - i2sodd_index) / 2;
if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
{
i2sodd_index = 0;
i2sdiv_index = 2;
}
spi_x->i2sclk_bit.i2sodd = i2sodd_index;
if(i2sdiv_index > 0x00FF)
{
spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
}
else
{
spi_x->i2sclk_bit.i2sdiv_h = 0;
spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
}
/* i2s audio_protocol set*/
if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
{
spi_x->i2sctrl_bit.pcmfssel = 1;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 3;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 2;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 1;
}
else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
{
spi_x->i2sctrl_bit.pcmfssel = 0;
spi_x->i2sctrl_bit.stdsel = 0;
}
/* i2s data_channel_format set*/
if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
{
spi_x->i2sctrl_bit.i2scbn = 0;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 0;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 1;
}
else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
{
spi_x->i2sctrl_bit.i2scbn = 1;
spi_x->i2sctrl_bit.i2sdbn = 2;
}
spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
spi_x->i2sctrl_bit.i2smsel = TRUE;
}
/**
* @brief enable or disable i2s.
* @param spi_x: select the i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of i2s.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void i2s_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->i2sctrl_bit.i2sen = new_state;
}
/**
* @brief enable or disable the specified spi/i2s interrupts.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - SPI_I2S_ERROR_INT
* - SPI_I2S_RDBF_INT
* - SPI_I2S_TDBE_INT
* @param new_state: new state of the specified spi/i2s interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
{
if(new_state != FALSE)
{
spi_x->ctrl2 |= spi_i2s_int;
}
else
{
spi_x->ctrl2 &= ~spi_i2s_int;
}
}
/**
* @brief enable or disable the spi/i2s dma transmitter mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaten = new_state;
}
/**
* @brief enable or disable the spi/i2s dma receiver mode.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param new_state: new state of the dma request.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
{
spi_x->ctrl2_bit.dmaren = new_state;
}
/**
* @brief spi/i2s data transmit
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param tx_data: the data to be transmit.
* this parameter can be:
* - (0x0000~0xFFFF)
* @retval none
*/
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
{
spi_x->dt = tx_data;
}
/**
* @brief spi/i2s data receive
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @retval the received data value
*/
uint16_t spi_i2s_data_receive(spi_type* spi_x)
{
return (uint16_t)spi_x->dt;
}
/**
* @brief get flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_ACS_FLAG (this flag only use in i2s mode)
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* - SPI_I2S_BF_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
if ((spi_x->sts & spi_i2s_flag) == RESET)
{
status = RESET;
}
else
{
status = SET;
}
return status;
}
/**
* @brief get interrupt flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
switch(spi_i2s_flag)
{
case SPI_I2S_RDBF_FLAG:
if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
{
status = SET;
}
break;
case SPI_I2S_TDBE_FLAG:
if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
{
status = SET;
}
break;
case I2S_TUERR_FLAG:
if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_CCERR_FLAG:
if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_MMERR_FLAG:
if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_I2S_ROERR_FLAG:
if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
default:
break;
};
return status;
}
/**
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_CCERR_FLAG
* - SPI_I2S_RDBF_FLAG
* - I2S_TUERR_FLAG
* - SPI_MMERR_FLAG
* - SPI_I2S_ROERR_FLAG
* @note
* SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
* I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
* SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
* @retval none
*/
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
{
if(spi_i2s_flag == SPI_CCERR_FLAG)
spi_x->sts = ~SPI_CCERR_FLAG;
else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
UNUSED(spi_x->dt);
else if(spi_i2s_flag == I2S_TUERR_FLAG)
UNUSED(spi_x->sts);
else if(spi_i2s_flag == SPI_MMERR_FLAG)
{
UNUSED(spi_x->sts);
spi_x->ctrl1 = spi_x->ctrl1;
}
else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
{
UNUSED(spi_x->dt);
UNUSED(spi_x->sts);
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_tmr.c
+1735
View File
File diff suppressed because it is too large Load Diff
DLD960LoopBootloader/libraries/drivers/src/at32f421_usart.c
+689
View File
@@ -0,0 +1,689 @@
/**
**************************************************************************
* @file at32f421_usart.c
* @brief contains all the functions for the usart firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup USART
* @brief USART driver modules
* @{
*/
#ifdef USART_MODULE_ENABLED
/** @defgroup USART_private_functions
* @{
*/
/**
* @brief deinitialize the usart peripheral registers to their default reset values.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval none
*/
void usart_reset(usart_type* usart_x)
{
if(usart_x == USART1)
{
crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
}
else if(usart_x == USART2)
{
crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
}
}
/**
* @brief initialize the usart peripheral according to the specified parameters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param baud_rate: configure the usart communication baud rate.
* @param data_bit: data bits transmitted or received in a frame
* this parameter can be one of the following values:
* - USART_DATA_8BITS
* - USART_DATA_9BITS.
* note：
* - when parity check is disabled, the data bit width is the actual data bit number.
* - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
* @param stop_bit: stop bits transmitted
* this parameter can be one of the following values:
* - USART_STOP_1_BIT
* - USART_STOP_0_5_BIT.
* - USART_STOP_2_BIT
* - USART_STOP_1_5_BIT.
* @retval none
*/
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
{
crm_clocks_freq_type clocks_freq;
uint32_t apb_clock, temp_val;
crm_clocks_freq_get(&clocks_freq);
if(usart_x == USART1)
{
apb_clock = clocks_freq.apb2_freq;
}
else
{
apb_clock = clocks_freq.apb1_freq;
}
temp_val = (apb_clock * 10 / baud_rate);
if((temp_val % 10) < 5)
{
temp_val = (temp_val / 10);
}
else
{
temp_val = (temp_val / 10) + 1;
}
usart_x->baudr_bit.div = temp_val;
usart_x->ctrl1_bit.dbn = data_bit;
usart_x->ctrl2_bit.stopbn = stop_bit;
}
/**
* @brief usart parity selection config.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param parity: select the none, odd or even parity.
* this parameter can be one of the following values:
* - USART_PARITY_NONE
* - USART_PARITY_EVEN.
* - USART_PARITY_ODD
* @retval none
*/
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
{
if(parity == USART_PARITY_NONE)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = FALSE;
}
else if(parity == USART_PARITY_EVEN)
{
usart_x->ctrl1_bit.psel = FALSE;
usart_x->ctrl1_bit.pen = TRUE;
}
else if(parity == USART_PARITY_ODD)
{
usart_x->ctrl1_bit.psel = TRUE;
usart_x->ctrl1_bit.pen = TRUE;
}
}
/**
* @brief enable or disable the specified usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.uen = new_state;
}
/**
* @brief usart transmitter enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ten = new_state;
}
/**
* @brief usart receiver enable.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE.
* @retval none
*/
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.ren = new_state;
}
/**
* @brief usart clock config.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param clk_pol: polarity of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_POLARITY_LOW
* - USART_CLOCK_POLARITY_HIGH
* @param clk_pha: phase of the clock output on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_PHASE_1EDGE
* - USART_CLOCK_PHASE_2EDGE
* @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
* this parameter can be one of the following values:
* - USART_CLOCK_LAST_BIT_NONE
* - USART_CLOCK_LAST_BIT_OUTPUT
* @retval none
*/
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
{
usart_x->ctrl2_bit.clkpol = clk_pol;
usart_x->ctrl2_bit.clkpha = clk_pha;
usart_x->ctrl2_bit.lbcp = clk_lb;
}
/**
* @brief usart enable the ck pin.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: TRUE or FALSE
* @retval none
*/
void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.clken = new_state;
}
/**
* @brief enable or disable the specified usart interrupts.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
* this parameter can be one of the following values:
* - USART_IDLE_INT: idle interrupt
* - USART_RDBF_INT: rdbf interrupt
* - USART_TDC_INT: tdc interrupt
* - USART_TDBE_INT: tdbe interrupt
* - USART_PERR_INT: perr interrupt
* - USART_BF_INT: break frame interrupt
* - USART_ERR_INT: err interrupt
* - USART_CTSCF_INT: ctscf interrupt
* @param new_state: new state of the specified usart interrupts.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
{
if(new_state == TRUE)
PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
else
PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
}
/**
* @brief enable or disable the usart's dma transmitter interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaten = new_state;
}
/**
* @brief enable or disable the usart's dma receiver interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the dma request sources.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.dmaren = new_state;
}
/**
* @brief set the wakeup id of the usart.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param usart_id: the matching id(0x0~0xF).
* @retval none
*/
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
{
usart_x->ctrl2_bit.id = usart_id;
}
/**
* @brief select the usart wakeup method in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param wakeup_mode: determines the way to wake up usart method.
* this parameter can be one of the following values:
* - USART_WAKEUP_BY_IDLE_FRAME
* - USART_WAKEUP_BY_MATCHING_ID
* @retval none
*/
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
{
usart_x->ctrl1_bit.wum = wakeup_mode;
}
/**
* @brief config the usart in mute mode in multi-processor communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart mute mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl1_bit.rm = new_state;
}
/**
* @brief set the usart break frame bit num.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param break_bit: specifies the break bit num.
* this parameter can be one of the following values:
* - USART_BREAK_10BITS
* - USART_BREAK_11BITS
* @retval none
*/
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
{
usart_x->ctrl2_bit.bfbn = break_bit;
}
/**
* @brief enable or disable the usart lin mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart lin mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.linen = new_state;
}
/**
* @brief transmit single data through the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param data: the data to transmit.
* @retval none
*/
void usart_data_transmit(usart_type* usart_x, uint16_t data)
{
usart_x->dt = (data & 0x01FF);
}
/**
* @brief return the most recent received data by the usart peripheral.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval the received data.
*/
uint16_t usart_data_receive(usart_type* usart_x)
{
return (uint16_t)(usart_x->dt);
}
/**
* @brief transmit break characters.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @retval none
*/
void usart_break_send(usart_type* usart_x)
{
usart_x->ctrl1_bit.sbf = TRUE;
}
/**
* @brief config the specified usart smartcard guard time.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param guard_time_val: specifies the guard time (0x00~0xFF).
* @retval none
*/
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
{
usart_x->gdiv_bit.scgt = guard_time_val;
}
/**
* @brief config the irda/smartcard division.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param div_val: specifies the division.
* @retval none
*/
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
{
usart_x->gdiv_bit.isdiv = div_val;
}
/**
* @brief enable or disable the usart smart card mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the smart card mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scmen = new_state;
}
/**
* @brief enable or disable nack transmission in smartcard mode.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the nack transmission.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.scnacken = new_state;
}
/**
* @brief enable or disable the usart single line bidirectional half-duplex communication.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the single line half-duplex select.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.slben = new_state;
}
/**
* @brief enable or disable the usart's irda interface.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdaen = new_state;
}
/**
* @brief configure the usart's irda low power.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl3_bit.irdalp = new_state;
}
/**
* @brief configure the usart's hardware flow control.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flow_state: specifies the hardware flow control.
* this parameter can be one of the following values:
* - USART_HARDWARE_FLOW_NONE
* - USART_HARDWARE_FLOW_RTS,
* - USART_HARDWARE_FLOW_CTS,
* - USART_HARDWARE_FLOW_RTS_CTS
* @retval none
*/
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
{
if(flow_state == USART_HARDWARE_FLOW_NONE)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = FALSE;
}
else if(flow_state == USART_HARDWARE_FLOW_CTS)
{
usart_x->ctrl3_bit.rtsen = FALSE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = TRUE;
}
}
/**
* @brief swap the usart's transmit receive pin.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param new_state: new state of the usart peripheral.
* this parameter can be: TRUE or FALSE.
* @retval none
*/
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
{
usart_x->ctrl2_bit.trpswap = new_state;
}
/**
* @brief check whether the specified usart flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
{
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief check whether the specified usart interrupt flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5)
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
{
flag_status int_status = RESET;
switch(flag)
{
case USART_CTSCF_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
break;
case USART_BFF_FLAG:
int_status = (flag_status)usart_x->ctrl2_bit.bfien;
break;
case USART_TDBE_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
break;
case USART_TDC_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
break;
case USART_RDBF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
break;
case USART_ROERR_FLAG:
int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
break;
case USART_IDLEF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
break;
case USART_NERR_FLAG:
case USART_FERR_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.errien;
break;
case USART_PERR_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
break;
default:
int_status = RESET;
break;
}
if(int_status != SET)
{
return RESET;
}
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear the usart's pending flags.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1 or USART2.
* @param flag: specifies the flag to clear.
* this parameter can be any combination of the following values:
* - USART_CTSCF_FLAG: (not available for UART4,UART5,USART6,UART7 and UART8).
* - USART_BFF_FLAG:
* - USART_TDC_FLAG:
* - USART_RDBF_FLAG:
* - USART_PERR_FLAG:
* - USART_FERR_FLAG:
* - USART_NERR_FLAG:
* - USART_ROERR_FLAG:
* - USART_IDLEF_FLAG:
* @note
* - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
* sequence: a read operation to usart sts register (usart_flag_get())
* followed by a read operation to usart dt register (usart_data_receive()).
* - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
* - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
* followed by a write operation to usart dt register (usart_data_transmit()).
* - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
* @retval none
*/
void usart_flag_clear(usart_type* usart_x, uint32_t flag)
{
if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
{
UNUSED(usart_x->sts);
UNUSED(usart_x->dt);
}
else
{
usart_x->sts = ~flag;
}
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_wdt.c
+143
View File
@@ -0,0 +1,143 @@
/**
**************************************************************************
* @file at32f421_wdt.c
* @brief contains all the functions for the wdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup WDT
* @brief WDT driver modules
* @{
*/
#ifdef WDT_MODULE_ENABLED
/** @defgroup WDT_private_functions
* @{
*/
/**
* @brief wdt enable ,the reload value will be sent to the counter
* @param none
* @retval none
*/
void wdt_enable(void)
{
WDT->cmd = WDT_CMD_ENABLE;
}
/**
* @brief reload wdt counter
* @param none
* @retval none
*/
void wdt_counter_reload(void)
{
WDT->cmd = WDT_CMD_RELOAD;
}
/**
* @brief set wdt counter reload value
* @param reload_value (0x0000~0x0FFF)
* @retval none
*/
void wdt_reload_value_set(uint16_t reload_value)
{
WDT->rld = reload_value;
}
/**
* @brief set wdt division divider
* @param division
* this parameter can be one of the following values:
* - WDT_CLK_DIV_4
* - WDT_CLK_DIV_8
* - WDT_CLK_DIV_16
* - WDT_CLK_DIV_32
* - WDT_CLK_DIV_64
* - WDT_CLK_DIV_128
* - WDT_CLK_DIV_256
* @retval none
*/
void wdt_divider_set(wdt_division_type division)
{
WDT->div_bit.div = division;
}
/**
* @brief enable or disable wdt cmd register write
* @param new_state (TRUE or FALSE)
* @retval none
*/
void wdt_register_write_enable( confirm_state new_state)
{
if(new_state == FALSE)
{
WDT->cmd = WDT_CMD_LOCK;
}
else
{
WDT->cmd = WDT_CMD_UNLOCK;
}
}
/**
* @brief get wdt flag
* @param wdt_flag
* this parameter can be one of the following values:
* - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
* - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
* @retval state of wdt flag
*/
flag_status wdt_flag_get(uint16_t wdt_flag)
{
flag_status status = RESET;
if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/libraries/drivers/src/at32f421_wwdt.c
+149
View File
@@ -0,0 +1,149 @@
/**
**************************************************************************
* @file at32f421_wwdt.c
* @brief contains all the functions for the wwdt firmware library
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_conf.h"
/** @addtogroup AT32F421_periph_driver
* @{
*/
/** @defgroup WWDT
* @brief WWDT driver modules
* @{
*/
#ifdef WWDT_MODULE_ENABLED
/** @defgroup WWDT_private_functions
* @{
*/
/**
* @brief wwdt reset by crm reset register
* @retval none
*/
void wwdt_reset(void)
{
crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
}
/**
* @brief wwdt division set
* @param division
* this parameter can be one of the following values:
* - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
* - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
* - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
* - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
* @retval none
*/
void wwdt_divider_set(wwdt_division_type division)
{
WWDT->cfg_bit.div = division;
}
/**
* @brief wwdt reload counter interrupt flag clear
* @param none
* @retval none
*/
void wwdt_flag_clear(void)
{
WWDT->sts = 0;
}
/**
* @brief wwdt enable and the counter value load
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_enable(uint8_t wwdt_cnt)
{
WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
}
/**
* @brief wwdt reload counter interrupt enable
* @param none
* @retval none
*/
void wwdt_interrupt_enable(void)
{
WWDT->cfg_bit.rldien = TRUE;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_flag_get(void)
{
return (flag_status)WWDT->sts_bit.rldf;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_interrupt_flag_get(void)
{
return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
}
/**
* @brief wwdt counter value set
* @param wwdt_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_counter_set(uint8_t wwdt_cnt)
{
WWDT->ctrl_bit.cnt = wwdt_cnt;
}
/**
* @brief wwdt window counter value set
* @param window_cnt (0x40~0x7f)
* @retval none
*/
void wwdt_window_counter_set(uint8_t window_cnt)
{
WWDT->cfg_bit.win = window_cnt;
}
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/project/at32f421_board/at32f421_board.c
+397
View File
@@ -0,0 +1,397 @@
/**
**************************************************************************
* @file at32f421_board.c
* @brief set of firmware functions to manage leds and push-button.
* initialize delay function.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_board.h"
/** @addtogroup AT32F421_board
* @{
*/
/** @defgroup BOARD
* @brief onboard periph driver
* @{
*/
/* delay macros */
#define STEP_DELAY_MS 50
/* at-start led resouce array */
gpio_type *led_gpio_port[LED_NUM] = {LED2_GPIO, LED3_GPIO, LED4_GPIO};
uint16_t led_gpio_pin[LED_NUM] = {LED2_PIN, LED3_PIN, LED4_PIN};
crm_periph_clock_type led_gpio_crm_clk[LED_NUM] = {LED2_GPIO_CRM_CLK, LED3_GPIO_CRM_CLK, LED4_GPIO_CRM_CLK};
/* delay variable */
static __IO uint32_t fac_us;
static __IO uint32_t fac_ms;
/* support printf function, usemicrolib is unnecessary */
#if (__ARMCC_VERSION > 6000000)
__asm (".global __use_no_semihosting\n\t");
void _sys_exit(int x)
{
x = x;
}
/* __use_no_semihosting was requested, but _ttywrch was */
void _ttywrch(int ch)
{
ch = ch;
}
FILE __stdout;
#else
#ifdef __CC_ARM
#pragma import(__use_no_semihosting)
struct __FILE
{
int handle;
};
FILE __stdout;
void _sys_exit(int x)
{
x = x;
}
/* __use_no_semihosting was requested, but _ttywrch was */
void _ttywrch(int ch)
{
ch = ch;
}
#endif
#endif
#if defined (__GNUC__) && !defined (__clang__)
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
#else
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#endif
/**
* @brief retargets the c library printf function to the usart.
* @param none
* @retval none
*/
PUTCHAR_PROTOTYPE
{
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, (uint16_t)ch);
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
return ch;
}
#if (defined (__GNUC__) && !defined (__clang__)) || (defined (__ICCARM__))
#if defined (__GNUC__) && !defined (__clang__)
int _write(int fd, char *pbuffer, int size)
#elif defined ( __ICCARM__ )
#pragma module_name = "?__write"
int __write(int fd, char *pbuffer, int size)
#endif
{
for(int i = 0; i < size; i ++)
{
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
usart_data_transmit(PRINT_UART, (uint16_t)(*pbuffer++));
while(usart_flag_get(PRINT_UART, USART_TDC_FLAG) == RESET);
}
return size;
}
#endif
/**
* @brief initialize uart
* @param baudrate: uart baudrate
* @retval none
*/
void uart_print_init(uint32_t baudrate)
{
gpio_init_type gpio_init_struct;
#if defined (__GNUC__) && !defined (__clang__)
setvbuf(stdout, NULL, _IONBF, 0);
#endif
/* enable the uart and gpio clock */
crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE);
crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE);
gpio_default_para_init(&gpio_init_struct);
/* configure the uart tx pin */
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct);
gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM);
/* configure uart param */
usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(PRINT_UART, TRUE);
usart_enable(PRINT_UART, TRUE);
}
/**
* @brief board initialize interface init led and button
* @param none
* @retval none
*/
void at32_board_init()
{
/* initialize delay function */
delay_init();
/* configure led in at_start_board */
at32_led_init(LED2);
at32_led_init(LED3);
at32_led_init(LED4);
at32_led_off(LED2);
at32_led_on(LED3);
at32_led_on(LED4);
/* configure button in at_start board */
// at32_button_init();
}
/**
* @brief configure button gpio
* @param button: specifies the button to be configured.
* @retval none
*/
void at32_button_init(void)
{
gpio_init_type gpio_init_struct;
/* enable the button clock */
crm_periph_clock_enable(USER_BUTTON_CRM_CLK, TRUE);
/* set default parameter */
gpio_default_para_init(&gpio_init_struct);
/* configure button pin as input with pull-up/pull-down */
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
gpio_init_struct.gpio_pins = USER_BUTTON_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
gpio_init(USER_BUTTON_PORT, &gpio_init_struct);
}
/**
* @brief returns the selected button state
* @param none
* @retval the button gpio pin value
*/
uint8_t at32_button_state(void)
{
return gpio_input_data_bit_read(USER_BUTTON_PORT, USER_BUTTON_PIN);
}
/**
* @brief returns which button have press down
* @param none
* @retval the button have press down
*/
button_type at32_button_press()
{
static uint8_t pressed = 1;
/* get button state in at_start board */
if((pressed == 1) && (at32_button_state() != RESET))
{
/* debounce */
pressed = 0;
delay_ms(10);
if(at32_button_state() != RESET)
return USER_BUTTON;
}
else if(at32_button_state() == RESET)
{
pressed = 1;
}
return NO_BUTTON;
}
/**
* @brief configure led gpio
* @param led: specifies the led to be configured.
* @retval none
*/
void at32_led_init(led_type led)
{
gpio_init_type gpio_init_struct;
/* enable the led clock */
crm_periph_clock_enable(led_gpio_crm_clk[led], TRUE);
/* set default parameter */
gpio_default_para_init(&gpio_init_struct);
/* configure the led gpio */
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
gpio_init_struct.gpio_pins = led_gpio_pin[led];
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(led_gpio_port[led], &gpio_init_struct);
}
/**
* @brief turns selected led on.
* @param led: specifies the led to be set on.
* this parameter can be one of following parameters:
* @arg LED2
* @arg LED3
* @arg LED4
* @retval none
*/
void at32_led_on(led_type led)
{
if(led > (LED_NUM - 1))
return;
if(led_gpio_pin[led])
led_gpio_port[led]->clr = led_gpio_pin[led];
}
/**
* @brief turns selected led off.
* @param led: specifies the led to be set off.
* this parameter can be one of following parameters:
* @arg LED2
* @arg LED3
* @arg LED4
* @retval none
*/
void at32_led_off(led_type led)
{
if(led > (LED_NUM - 1))
return;
if(led_gpio_pin[led])
led_gpio_port[led]->scr = led_gpio_pin[led];
}
/**
* @brief turns selected led toggle.
* @param led: specifies the led to be set off.
* this parameter can be one of following parameters:
* @arg LED2
* @arg LED3
* @arg LED4
* @retval none
*/
void at32_led_toggle(led_type led)
{
if(led > (LED_NUM - 1))
return;
if(led_gpio_pin[led])
led_gpio_port[led]->odt ^= led_gpio_pin[led];
}
/**
* @brief initialize delay function
* @param none
* @retval none
*/
void delay_init()
{
/* configure systick */
systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV);
fac_us = system_core_clock / (1000000U);
fac_ms = fac_us * (1000U);
}
/**
* @brief inserts a delay time.
* @param nus: specifies the delay time length, in microsecond.
* @retval none
*/
void delay_us(uint32_t nus)
{
uint32_t temp = 0;
SysTick->LOAD = (uint32_t)(nus * fac_us);
SysTick->VAL = 0x00;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ;
do
{
temp = SysTick->CTRL;
}while((temp & 0x01) && !(temp & (1 << 16)));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->VAL = 0x00;
}
/**
* @brief inserts a delay time.
* @param nms: specifies the delay time length, in milliseconds.
* @retval none
*/
void delay_ms(uint16_t nms)
{
uint32_t temp = 0;
while(nms)
{
if(nms > STEP_DELAY_MS)
{
SysTick->LOAD = (uint32_t)(STEP_DELAY_MS * fac_ms);
nms -= STEP_DELAY_MS;
}
else
{
SysTick->LOAD = (uint32_t)(nms * fac_ms);
nms = 0;
}
SysTick->VAL = 0x00;
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
do
{
temp = SysTick->CTRL;
}while((temp & 0x01) && !(temp & (1 << 16)));
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->VAL = 0x00;
}
}
/**
* @brief inserts a delay time.
* @param sec: specifies the delay time, in seconds.
* @retval none
*/
void delay_sec(uint16_t sec)
{
uint16_t index;
for(index = 0; index < sec; index++)
{
delay_ms(500);
delay_ms(500);
}
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/project/at32f421_board/at32f421_board.h
+150
View File
@@ -0,0 +1,150 @@
/**
**************************************************************************
* @file at32f421_board.h
* @brief header file for at-start board. set of firmware functions to
* manage leds and push-button. initialize delay function.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __AT32F421_BOARD_H
#define __AT32F421_BOARD_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stdio.h"
#include "at32f421.h"
/** @addtogroup AT32F421_board
* @{
*/
/** @addtogroup BOARD
* @{
*/
/** @defgroup BOARD_pins_definition
* @{
*/
/**
* this header include define support list:
* 1. at-start-f421 v1.x boards
* if define AT_START_F421_V1, the header file support at-start-f421 v1.x board
*/
#if !defined (AT_START_F421_V1)
#error "please select first the board at-start device used in your application (in at32f421_board.h file)"
#endif
/******************** define led ********************/
typedef enum
{
LED2 = 0,
LED3 = 1,
LED4 = 2
} led_type;
#define LED_NUM 3
#if defined (AT_START_F421_V1)
#define LED2_PIN GPIO_PINS_5
#define LED2_GPIO GPIOA
#define LED2_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
#define LED3_PIN GPIO_PINS_4
#define LED3_GPIO GPIOA
#define LED3_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
#define LED4_PIN GPIO_PINS_8
#define LED4_GPIO GPIOA
#define LED4_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
#endif
/**************** define print uart ******************/
#define PRINT_UART USART1
#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK
#define PRINT_UART_TX_PIN GPIO_PINS_9
#define PRINT_UART_TX_GPIO GPIOA
#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9
#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_1
/******************* define button *******************/
typedef enum
{
USER_BUTTON = 0,
NO_BUTTON = 1
} button_type;
#define USER_BUTTON_PIN GPIO_PINS_0
#define USER_BUTTON_PORT GPIOA
#define USER_BUTTON_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
/**
* @}
*/
/** @defgroup BOARD_exported_functions
* @{
*/
/******************** functions ********************/
void at32_board_init(void);
/* led operation function */
void at32_led_init(led_type led);
void at32_led_on(led_type led);
void at32_led_off(led_type led);
void at32_led_toggle(led_type led);
/* button operation function */
void at32_button_init(void);
button_type at32_button_press(void);
uint8_t at32_button_state(void);
/* delay function */
void delay_init(void);
void delay_us(uint32_t nus);
void delay_ms(uint16_t nms);
void delay_sec(uint16_t sec);
/* printf uart init function */
void uart_print_init(uint32_t baudrate);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/at32f421_clock.h
+44
View File
@@ -0,0 +1,44 @@
/**
**************************************************************************
* @file at32f421_clock.h
* @brief header file of clock program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_CLOCK_H
#define __AT32F421_CLOCK_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/* exported functions ------------------------------------------------------- */
void system_clock_config(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT32F421_CLOCK_H */
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/at32f421_conf.h
+137
View File
@@ -0,0 +1,137 @@
/**
**************************************************************************
* @file at32f421_conf.h
* @brief at32f421 config header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_CONF_H
#define __AT32F421_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief in the following line adjust the value of high speed external crystal (hext)
* used in your application
*
* tip: to avoid modifying this file each time you need to use different hext, you
* can define the hext value in your toolchain compiler preprocessor.
*
*/
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)12000000) /*!< value of the high speed external crystal in hz */
#endif
/**
* @brief in the following line adjust the high speed external crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED
#define CMP_MODULE_ENABLED
#define TMR_MODULE_ENABLED
#define ERTC_MODULE_ENABLED
#define GPIO_MODULE_ENABLED
#define I2C_MODULE_ENABLED
#define USART_MODULE_ENABLED
#define PWC_MODULE_ENABLED
#define ADC_MODULE_ENABLED
#define SPI_MODULE_ENABLED
#define DMA_MODULE_ENABLED
#define DEBUG_MODULE_ENABLED
#define FLASH_MODULE_ENABLED
#define CRC_MODULE_ENABLED
#define WWDT_MODULE_ENABLED
#define WDT_MODULE_ENABLED
#define EXINT_MODULE_ENABLED
#define MISC_MODULE_ENABLED
#define SCFG_MODULE_ENABLED
/* includes ------------------------------------------------------------------*/
#ifdef CRM_MODULE_ENABLED
#include "at32f421_crm.h"
#endif
#ifdef CMP_MODULE_ENABLED
#include "at32f421_cmp.h"
#endif
#ifdef TMR_MODULE_ENABLED
#include "at32f421_tmr.h"
#endif
#ifdef ERTC_MODULE_ENABLED
#include "at32f421_ertc.h"
#endif
#ifdef GPIO_MODULE_ENABLED
#include "at32f421_gpio.h"
#endif
#ifdef I2C_MODULE_ENABLED
#include "at32f421_i2c.h"
#endif
#ifdef USART_MODULE_ENABLED
#include "at32f421_usart.h"
#endif
#ifdef PWC_MODULE_ENABLED
#include "at32f421_pwc.h"
#endif
#ifdef ADC_MODULE_ENABLED
#include "at32f421_adc.h"
#endif
#ifdef SPI_MODULE_ENABLED
#include "at32f421_spi.h"
#endif
#ifdef DMA_MODULE_ENABLED
#include "at32f421_dma.h"
#endif
#ifdef DEBUG_MODULE_ENABLED
#include "at32f421_debug.h"
#endif
#ifdef FLASH_MODULE_ENABLED
#include "at32f421_flash.h"
#endif
#ifdef CRC_MODULE_ENABLED
#include "at32f421_crc.h"
#endif
#ifdef WWDT_MODULE_ENABLED
#include "at32f421_wwdt.h"
#endif
#ifdef WDT_MODULE_ENABLED
#include "at32f421_wdt.h"
#endif
#ifdef EXINT_MODULE_ENABLED
#include "at32f421_exint.h"
#endif
#ifdef MISC_MODULE_ENABLED
#include "at32f421_misc.h"
#endif
#ifdef SCFG_MODULE_ENABLED
#include "at32f421_scfg.h"
#endif
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/at32f421_int.h
+56
View File
@@ -0,0 +1,56 @@
/**
**************************************************************************
* @file at32f421_int.h
* @brief header file of main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32F421_INT_H
#define __AT32F421_INT_H
#ifdef __cplusplus
extern "C" {
#endif
/* includes ------------------------------------------------------------------*/
#include "at32f421.h"
/* exported types ------------------------------------------------------------*/
/* exported constants --------------------------------------------------------*/
/* exported macro ------------------------------------------------------------*/
/* exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/flash.h
+78
View File
@@ -0,0 +1,78 @@
/**
**************************************************************************
* @file flash.h
* @brief flash header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __FLASH_H__
#define __FLASH_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "at32f421_board.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/** @defgroup bootloader_definition
* @{
*/
#define FLASH_SIZE (*((uint32_t*)0x1FFFF7E0)) /* read from at32 flash capacity register(unit:kbyte) */
#define SRAM_SIZE 16 /* sram size, unit:kbyte */
/**
* @}
*/
/** @defgroup bootloader_exported_functions
* @{
*/
void flash_2kb_write(uint32_t write_addr, uint8_t *pbuffer);
void flash_write_by_sea_and_len(uint32_t write_addr, uint8_t *pbuffer, uint16_t byte_len); // add by wfq 230419
void flash_2kb_write_by_addr(uint32_t dst_addr, uint32_t ori_addr); // add by wfq 230415
flag_status flash_upgrade_flag_read(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/iap.h
+227
View File
@@ -0,0 +1,227 @@
/**
**************************************************************************
* @file iap.h
* @brief iap header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __IAP_H__
#define __IAP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "at32f421_board.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/** @defgroup bootloader_definition
* @{
*/
/* app starting address */
#define APP_START_ADDR 0x08003400
/* the previous sector of app starting address is iap upgrade flag */
#define IAP_UPGRADE_FLAG_ADDR (APP_START_ADDR - 0x800)
#define UPGRADE_DAT_START_ADDR APP_START_ADDR //0x0800A000 // 0x0804B000 // 0x08080000
/* when app received cmd 0x5aa5 from pc-tool, will set up the flag,
indicates that an app upgrade will follow, see iap application note for more details */
#define IAP_UPGRADE_FLAG 0x41544B38
#define IAP_UPGRADE_FLAG_9F 0x444C4439 //0x41544B39 //use 9F Protocol
#define IAP_UPGRADE_TYPE_DEFAULT 0
#define IAP_UPGRADE_TYPE_9F 1
#define IAP_CMD_READY 0xA5
#define IAP_CMD_ADDR_START 0xA6
#define IAP_CMD_TRAN_PKG_WITH_BACK 0xA7
#define IAP_CMD_TRAN_PKG_WITHOUT_OKBACK 0xA8
extern char g_flag_iap_upgrade_type;
/**
* @}
*/
/** @defgroup bootloader_exported_types
* @{
*/
/**
* @brief cmd data group type
*/
typedef struct
{
uint8_t cmd_head;
uint8_t cmd_addr[4];
uint8_t cmd_buf[0x800];
uint8_t cmd_check;
} cmd_data_group_type;
typedef struct
{
uint8_t cmd_head;
uint8_t cmd_addr[4];
uint8_t cmd_buf[0x800];
uint8_t cmd_check;
uint16_t offset;
uint16_t amount;
uint16_t sector_num; //0,1, ...
uint32_t write_addr;
} CMD_DATA_GROUP_ACT_TYPE;
/**
* @brief cmd data step type
*/
typedef enum
{
CMD_DATA_IDLE,
CMD_DATA_ADDR,
CMD_DATA_BUF,
CMD_DATA_CHACK,
CMD_DATA_DONE,
CMD_DATA_ERR,
} cmd_data_step_type;
/**
* @brief cmd ctr step type
*/
typedef enum
{
CMD_CTR_IDLE,
CMD_CTR_INIT,
CMD_CTR_DONE,
CMD_CTR_ERR,
CMD_CTR_APP,
} cmd_ctr_step_type;
/**
* @brief update status type
*/
typedef enum
{
UPDATE_PRE,
UPDATE_CLEAR_FLAG,
UPDATE_ING,
UPDATE_DONE,
DGCMD_FLAG, // 0x7F header
DGCMD_ING,
DGCMD_DONE,
} update_status_type;
typedef void (*iapfun)(void);
typedef enum
{
CMD_STATUS_9F_OK = 0,
CMD_STATUS_9F_Err,
} CMD_9F_STATUS;
typedef enum
{
CMD_9F_DATA_IDLE,
CMD_9F_DATA_HEADER,
CMD_9F_DATA_SUB_AMOUNT,
CMD_9F_DATA_LEN,
CMD_9F_DATA_CMD,
CMD_9F_DATA_ADDR,
CMD_9F_DATA_BUF,
CMD_9F_PRE_CHACK,
CMD_9F_ADDR_CHACK,
CMD_9F_DATA_CHACK,
CMD_9F_ADDR_DONE,
CMD_9F_DATA_DONE,
CMD_9F_ADDR_ERR,
CMD_9F_DATA_ERR,
CMD_9F_DATA_BUF_WITHOUT_BACK,
CMD_9F_DATA_CHACK_WITHOUT_BACK,
CMD_9F_DATA_DONE_WITHOUT_BACK,
CMD_9F_DATA_ERR_WITHOUT_BACK,
} cmd_9f_data_step_type;
typedef enum
{
CMD_7F_DATA_IDLE = 0,
CMD_7F_DATA_HEADER, // offset = 0
CMD_7F_DATA_ADDR,
CMD_7F_DATA_LEN,
CMD_7F_DATA_CMD,
CMD_7F_DATA_DAT,
CMD_7F_DATA_CHECK_XOR,
CMD_7F_DATA_CHECK_SUM,
CMD_7F_DATA_DONE,
CMD_7F_DATA_ERR,
} cmd_7f_data_step_type;
/**
* @}
*/
extern cmd_data_group_type cmd_data_group_type_struct;
extern CMD_DATA_GROUP_ACT_TYPE g_cmd_data_group_act;
extern cmd_data_step_type cmd_data_step;
extern cmd_ctr_step_type cmd_ctr_step;
extern update_status_type update_status;
/** @defgroup bootloader_exported_functions
* @{
*/
void back_9F_pre_ok(void);
void back_err(void);
void iap_upgrade_app_handle(void);
void iap_upgrade_app_9F_handle(void);
void app_load(uint32_t appxaddr);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/tmr.h
+67
View File
@@ -0,0 +1,67 @@
/**
**************************************************************************
* @file tmr.h
* @brief tmr header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __TMR_H
#define __TMR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "at32f421_board.h"
extern uint8_t time_ira_cnt;
extern uint8_t get_data_from_usart_flag;
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/** @defgroup bootloader_exported_functions
* @{
*/
void tmr_init(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/inc/usart.h
+161
View File
@@ -0,0 +1,161 @@
/**
**************************************************************************
* @file usart.h
* @brief usart header file
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __USART_H
#define __USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "at32f421_board.h"
#define SOFTWARE_H 0
#define SOFTWARE_L 7
#define HARDWARE_H 1
#define HARDWARE_L 0
/** @addtogroup UTILITIES_examples
* @{
*/
#define CPU_ID_BASE_ADDR (uint32_t*)(0x1FFFF7E8)
typedef struct __CPU_INFO__
{
union{
uint8_t byte[12];
uint32_t id[3];
}info;
}cpu_t;
/** @addtogroup DG_CMD, header: 0x7F
* @{
*/
#define RESET_RADAR_LOOP 0X6D
#define RESET_RADAR_LOOP_RETURN 0X6E
#define ENABLE_BLUETOOTH 0X9E
#define BLUETOOTH_CONNECTION_STATUS 0X9F
#define GET_RADAR_EQUIPMENT 0XA0
#define CLEAR_RADAR_BACKGROUND 0XA1
/** @addtogroup USART_iap_bootloader
* @{
*/
/** @defgroup bootloader_definition
* @{
*/
#define USART_REC_LEN 1024
/**
* @}
*/
/** @defgroup bootloader_exported_types
* @{
*/
/**
* @brief usart group type
*/
typedef struct
{
uint16_t buf[USART_REC_LEN];
uint16_t head;
uint16_t tail;
uint16_t count;
} usart_group_type;
#define MAX_UART_TXRX_LEN 32
#define BT_RCV_TIME_OUT_MS 20 //20ms
typedef struct _DUART_BUF_
{
uint8_t header;
uint8_t addr;
uint8_t len;
uint8_t cmd;
uint8_t buf[MAX_UART_TXRX_LEN];
uint8_t ckb_xor;
uint8_t ckb_sum;
uint8_t index;
}Duart_Buf;
extern Duart_Buf g_uart_buf_7f;
#define MAX_COM_UART_DAT_LEN 64
typedef struct
{
unsigned char head;
unsigned char addr;
unsigned char len;
unsigned char cmd;
unsigned char dat[MAX_COM_UART_DAT_LEN];
// unsigned char loop_sensitivity;
// unsigned char loop_cut;
// unsigned char loop_car;
// unsigned char loop_Frequency1;
// unsigned char loop_Frequency2;
// unsigned char loop_Frequency3;
unsigned char xor;
unsigned char sum;
}comStruct;
/**
* @}
*/
extern usart_group_type usart_group_struct;
/** @defgroup bootloader_exported_functions
* @{
*/
extern uint8_t g_device_id[6];
void get_cpu_id(void);
void uart_init(uint32_t baudrate);
void uart1_send_buf(uint8_t *buf, uint8_t len);
comStruct usart_packet_processing(uint8_t cmd, void *buff, uint8_t LEN);
void Com_Return_rader_para(comStruct para);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/at32f421_clock.c
+97
View File
@@ -0,0 +1,97 @@
/**
**************************************************************************
* @file at32f421_clock.c
* @brief system clock config program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_clock.h"
/**
* @brief system clock config program
* @note the system clock is configured as follow:
* system clock (sclk) = hext * pll_mult
* system clock source = pll (hext)
* - hext = HEXT_VALUE
* - sclk = 120000000
* - ahbdiv = 1
* - ahbclk = 120000000
* - apb2div = 1
* - apb2clk = 120000000
* - apb1div = 1
* - apb1clk = 120000000
* - pll_mult = 15
* - flash_wtcyc = 3 cycle
* @param none
* @retval none
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* config flash psr register */
flash_psr_set(FLASH_WAIT_CYCLE_3);
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
/* config pll clock resource */
crm_pll_config(CRM_PLL_SOURCE_HEXT, CRM_PLL_MULT_10);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 120 MHz */
crm_apb2_div_set(CRM_APB2_DIV_1);
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 120 MHz */
crm_apb1_div_set(CRM_APB1_DIV_1);
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
}
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/at32f421_int.c
+139
View File
@@ -0,0 +1,139 @@
/**
**************************************************************************
* @file at32f421_int.c
* @brief main interrupt service routines.
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
/* includes ------------------------------------------------------------------*/
#include "at32f421_int.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/**
* @brief this function handles nmi exception.
* @param none
* @retval none
*/
void NMI_Handler(void)
{
}
/**
* @brief this function handles hard fault exception.
* @param none
* @retval none
*/
void HardFault_Handler(void)
{
/* go to infinite loop when hard fault exception occurs */
while (1)
{
}
}
/**
* @brief this function handles memory manage exception.
* @param none
* @retval none
*/
void MemManage_Handler(void)
{
/* go to infinite loop when memory manage exception occurs */
while (1)
{
}
}
/**
* @brief this function handles bus fault exception.
* @param none
* @retval none
*/
void BusFault_Handler(void)
{
/* go to infinite loop when bus fault exception occurs */
while (1)
{
}
}
/**
* @brief this function handles usage fault exception.
* @param none
* @retval none
*/
void UsageFault_Handler(void)
{
/* go to infinite loop when usage fault exception occurs */
while (1)
{
}
}
/**
* @brief this function handles svcall exception.
* @param none
* @retval none
*/
void SVC_Handler(void)
{
}
/**
* @brief this function handles debug monitor exception.
* @param none
* @retval none
*/
void DebugMon_Handler(void)
{
}
/**
* @brief this function handles pendsv_handler exception.
* @param none
* @retval none
*/
void PendSV_Handler(void)
{
}
/**
* @brief this function handles systick handler.
* @param none
* @retval none
*/
void SysTick_Handler(void)
{
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/flash.c
+125
View File
@@ -0,0 +1,125 @@
/**
**************************************************************************
* @file flash.c
* @brief flash program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "flash.h"
#include "usart.h"
#include "iap.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/**
* @brief flash erase/program operation.
* @note follow 2kb operation of ont time
* @param none
* @retval none
*/
void flash_2kb_write(uint32_t write_addr, uint8_t *pbuffer)
{
uint16_t index, write_data;
flash_unlock();
flash_sector_erase(write_addr);
if(FLASH_SIZE < 0x100) /* less than 256kb, 1kb/sector */
flash_sector_erase(write_addr + 0x400);
for(index = 0; index < 2048; index += 2)
{
write_data = (pbuffer[index+1] << 8) + pbuffer[index];
flash_halfword_program(write_addr, write_data);
write_addr += sizeof(uint16_t);
}
flash_lock();
}
void flash_write_by_sea_and_len(uint32_t write_addr, uint8_t *pbuffer, uint16_t byte_len)
{
uint16_t index, write_data;
flash_unlock();
flash_sector_erase(write_addr);
if(FLASH_SIZE < 0x100) /* less than 256kb, 1kb/sector */
flash_sector_erase(write_addr + 0x400);
for(index = 0; index < byte_len; index += 2)
{
write_data = (pbuffer[index+1] << 8) + pbuffer[index];
flash_halfword_program(write_addr, write_data);
write_addr += sizeof(uint16_t);
}
flash_lock();
}
/**
* @brief flash erase/program operation.
* @note follow 2kb operation of ont time
* @param none
* @retval none
*/
void flash_2kb_write_by_addr(uint32_t dst_addr, uint32_t ori_addr)
{
uint32_t index;
uint32_t _dst_addr = dst_addr;
uint32_t _ori_addr = ori_addr;
flash_unlock();
flash_sector_erase(dst_addr);
if(FLASH_SIZE < 0x100) /* less than 256kb, 1kb/sector */
flash_sector_erase(dst_addr + 0x400);
for(index = 0; index < 2048; index += 4)
{
flash_word_program(_dst_addr, (*(uint32_t *)_ori_addr));
_dst_addr += sizeof(uint32_t);
_ori_addr += sizeof(uint32_t);
}
flash_lock();
}
/**
* @brief check flash upgrade flag.
* @param none
* @retval none
*/
flag_status flash_upgrade_flag_read(void)
{
if((*(uint32_t*)IAP_UPGRADE_FLAG_ADDR) == IAP_UPGRADE_FLAG_9F)
{
g_flag_iap_upgrade_type = IAP_UPGRADE_TYPE_9F;
return SET;
}
else
return RESET;
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/iap.c
+814
View File
@@ -0,0 +1,814 @@
/**
**************************************************************************
* @file iap.c
* @brief iap program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include <string.h>
#include "iap.h"
#include "usart.h"
#include "flash.h"
#include "tmr.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
cmd_data_step_type cmd_data_step = CMD_DATA_IDLE;
cmd_9f_data_step_type cmd_data_9f_step = CMD_9F_DATA_IDLE;
cmd_ctr_step_type cmd_ctr_step = CMD_CTR_IDLE;
cmd_7f_data_step_type cmd_data_7f_step = CMD_7F_DATA_IDLE;
cmd_data_group_type cmd_data_group_struct;
CMD_DATA_GROUP_ACT_TYPE g_cmd_data_group_act;
update_status_type update_status = UPDATE_PRE;
static uint8_t cmd_addr_cnt = 0;
static uint32_t cmd_data_cnt = 0;
iapfun jump_to_app;
//9f
uint16_t g_sub_amount_current = 0;
uint8_t g_sub_amount_cnt = 0;
uint16_t g_pkg_dat_len = 0;
uint16_t g_pkg_dat_cnt = 0;
uint8_t g_pkg_cmd = 0;
uint32_t g_cmd_base_addr = 0;
uint16_t g_amount_sector = 0; // 1 sector contain 2048 Byte = 0x800 byte
char g_flag_iap_upgrade_type = 0;
static unsigned char Device_Name[12] ={ 'D', 'L','D','9', '6','0','G','A'};
static unsigned char RS485_ID = 1; //485µؖ·
//0x7F
Duart_Buf g_uart_buf_7f = {0,};
uint8_t g_key_press_enable_ble = 0;
uint8_t Enable_Bluetooth_flag = 0;
/* app_load don't optimize */
#if defined (__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
__attribute__((optnone))
#else
#pragma O0
#endif
#elif defined (__ICCARM__)
#pragma optimize=s none
#elif defined (__GNUC__)
__attribute__((optimize("O0")))
#endif
/**
* @brief app load.
* @param app_addr
* app code starting address
* @retval none
*/
void app_load(uint32_t app_addr)
{
/* check the address of stack */
if(((*(uint32_t*)app_addr) - 0x20000000) <= (SRAM_SIZE * 1024))
{
/* disable periph clock */
crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, FALSE);
crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK, FALSE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, FALSE);
/* disable nvic irq and clear pending */
nvic_irq_disable(USART1_IRQn);
nvic_irq_disable(TMR3_GLOBAL_IRQn);
__NVIC_ClearPendingIRQ(USART1_IRQn);
__NVIC_ClearPendingIRQ(TMR3_GLOBAL_IRQn);
jump_to_app = (iapfun)*(uint32_t*)(app_addr + 4); /* code second word is reset address */
__set_MSP(*(uint32_t*)app_addr); /* init app stack pointer(code first word is stack address) */
jump_to_app(); /* jump to user app */
}
}
/**
* @brief take data from usart buf.
* @param app_addr
* app code starting address
* @retval val
* took data
*/
uint8_t data_take(void)
{
uint8_t val;
usart_interrupt_enable(USART1, USART_RDBF_INT, FALSE);
usart_group_struct.count--;
usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
val = usart_group_struct.buf[usart_group_struct.tail++];
if(usart_group_struct.tail > (USART_REC_LEN-1))
usart_group_struct.tail = 0;
return val;
}
void back_9F_pre_ok(void)
{ // 0xA5 upgrade pre
usart_data_transmit(USART1, 0x9F);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x01);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x00);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x02);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA5);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x00);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA8);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
void back_9F_addr_ok(void)
{// 0xA6
usart_data_transmit(USART1, 0x9F);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x01);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x00);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x02);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA6);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x00);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA9);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
void back_9F_addr_err(void)
{// 0xA6
usart_data_transmit(USART1, 0x9F);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x01);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x00);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x02);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA6);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x01);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xAA);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
/**
* @brief command response ok.
* @param sub_amount(current pkg received sub_amount), status(0 ok, 1 failed)
* @retval none
*/
void back_9F_data(uint16_t sub_amount, uint8_t status)
{// 0xA7
uint8_t _amount_low = (uint8_t)sub_amount;
uint8_t _amount_high = (uint8_t)(sub_amount>>8);
usart_data_transmit(USART1, 0x9F);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, _amount_low);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, _amount_high);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x02);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xA7);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, status);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, (uint8_t)(_amount_low + _amount_high + 0x02 + 0xA7 + status)); //check
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
void back_9F_data_cmd(uint8_t cmd, uint16_t sub_amount, uint8_t status)
{// 0xA7
uint8_t _amount_low = (uint8_t)sub_amount;
uint8_t _amount_high = (uint8_t)(sub_amount>>8);
usart_data_transmit(USART1, 0x9F);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, _amount_low);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, _amount_high);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0x02);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, cmd);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, status);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, (uint8_t)(_amount_low + _amount_high + 0x02 + cmd + status)); //check
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
void command_9f_handle(void)
{
uint8_t val, checksum, checkxor;
uint16_t index;
/* check whether received usart data */
if(usart_group_struct.count > 0)
val = data_take();
else
return;
if(update_status == UPDATE_PRE)
{
if(cmd_data_9f_step == CMD_9F_DATA_IDLE && cmd_data_7f_step == CMD_7F_DATA_IDLE)
{
if(val == 0x9F)
{
//header
update_status = UPDATE_ING;
}
else if(val == 0x7F)
{
update_status = DGCMD_ING;
cmd_data_7f_step = CMD_7F_DATA_IDLE;
}
}
}
if(update_status == DGCMD_ING)
{
switch(cmd_data_7f_step)
{
case CMD_7F_DATA_IDLE:
{
if(val == 0x7F)
{
cmd_data_7f_step = CMD_7F_DATA_HEADER;
g_uart_buf_7f.header = val;
g_uart_buf_7f.len = 0;
g_uart_buf_7f.cmd = 0;
g_uart_buf_7f.index = 0;
}
} break;
case CMD_7F_DATA_HEADER:
{
g_uart_buf_7f.addr = val;
cmd_data_7f_step = CMD_7F_DATA_ADDR;
} break;
case CMD_7F_DATA_ADDR:
{
g_uart_buf_7f.len = val;
cmd_data_7f_step = CMD_7F_DATA_LEN;
} break;
case CMD_7F_DATA_LEN:
{
g_uart_buf_7f.cmd = val;
//cmd_data_7f_step = CMD_7F_DATA_CMD;
if(g_uart_buf_7f.len == 1)
{
cmd_data_7f_step = CMD_7F_DATA_CHECK_XOR;
}
else
{
cmd_data_7f_step = CMD_7F_DATA_DAT;
}
} break;
// case CMD_7F_DATA_CMD:
// {
// g_uart_buf_7f.buf[0] = val;
// } break;
case CMD_7F_DATA_DAT:
{
g_uart_buf_7f.buf[g_uart_buf_7f.index] = val;
g_uart_buf_7f.index++;
if(g_uart_buf_7f.index >= (g_uart_buf_7f.len - 1))
{
cmd_data_7f_step = CMD_7F_DATA_CHECK_XOR;
}
} break;
case CMD_7F_DATA_CHECK_XOR:
{
g_uart_buf_7f.ckb_xor = val;
cmd_data_7f_step = CMD_7F_DATA_CHECK_SUM;
} break;
case CMD_7F_DATA_CHECK_SUM:
{
g_uart_buf_7f.ckb_sum = val;
checksum = g_uart_buf_7f.addr + g_uart_buf_7f.len + g_uart_buf_7f.cmd;
checkxor = g_uart_buf_7f.addr ^ g_uart_buf_7f.len ^ g_uart_buf_7f.cmd;
for(index = 0; index < (g_uart_buf_7f.len - 1); index++)
{
checksum += g_uart_buf_7f.buf[index];
checkxor ^= g_uart_buf_7f.buf[index];
}
checksum %= 0x100;
if(checkxor == g_uart_buf_7f.ckb_xor && checksum == g_uart_buf_7f.ckb_sum)
{
cmd_data_7f_step = CMD_7F_DATA_DONE;
}
else
{
cmd_data_7f_step = CMD_7F_DATA_ERR;
}
} break;
}
}// end if DGCMD_ING
else if(update_status == UPDATE_ING)
{
switch(cmd_data_9f_step)
{
case CMD_9F_DATA_IDLE:
{
if(val == 0x9F)
{
cmd_data_9f_step = CMD_9F_DATA_HEADER;
g_sub_amount_cnt = 0;
g_sub_amount_current = 0;
g_pkg_dat_cnt = 0;
g_pkg_dat_len = 0;
g_pkg_cmd = 0;
}
} break;
case CMD_9F_DATA_HEADER:
{
if(g_sub_amount_cnt == 0)
{
g_sub_amount_current = val;
}
else
{
g_sub_amount_current |= (val<<8);
}
g_sub_amount_cnt++;
if(g_sub_amount_cnt >= 2)
{
g_sub_amount_cnt = 0;
cmd_data_9f_step = CMD_9F_DATA_LEN;
}
} break;
case CMD_9F_DATA_LEN:
{
g_pkg_dat_len = val - 1; // minus cmd len
cmd_data_9f_step = CMD_9F_DATA_CMD;
} break;
case CMD_9F_DATA_CMD:
{
g_pkg_cmd = val;
if(g_pkg_cmd == IAP_CMD_READY)
{
cmd_data_9f_step = CMD_9F_PRE_CHACK;
}
else if(g_pkg_cmd == IAP_CMD_ADDR_START)
{
cmd_data_9f_step = CMD_9F_DATA_ADDR;
cmd_addr_cnt = 0;
}
else if(g_pkg_cmd == IAP_CMD_TRAN_PKG_WITH_BACK)
{
if(g_pkg_dat_len > 0)
{
cmd_data_9f_step = CMD_9F_DATA_BUF;
}
else
{
cmd_data_9f_step = CMD_9F_DATA_CHACK;
}
cmd_data_cnt = 0;
}
else if(g_pkg_cmd == IAP_CMD_TRAN_PKG_WITHOUT_OKBACK)
{
if(g_pkg_dat_len > 0)
{
cmd_data_9f_step = CMD_9F_DATA_BUF_WITHOUT_BACK;
}
else
{
cmd_data_9f_step = CMD_9F_DATA_CHACK_WITHOUT_BACK;
}
cmd_data_cnt = 0;
}
} break;
case CMD_9F_DATA_ADDR:
{
cmd_data_group_struct.cmd_addr[cmd_addr_cnt] = val;
cmd_addr_cnt++;
if(cmd_addr_cnt >= 4)
{
cmd_addr_cnt = 0;
cmd_data_9f_step = CMD_9F_ADDR_CHACK;
// printf("Rcv_addr: %02X%02X%02X%02X\n", cmd_data_group_struct.cmd_addr[0],cmd_data_group_struct.cmd_addr[1],cmd_data_group_struct.cmd_addr[2],cmd_data_group_struct.cmd_addr[3]);
}
} break;
case CMD_9F_DATA_BUF:
{
cmd_data_group_struct.cmd_buf[cmd_data_cnt] = val;
cmd_data_cnt++;
if(cmd_data_cnt >= g_pkg_dat_len)
{
cmd_data_cnt = 0;
cmd_data_9f_step = CMD_9F_DATA_CHACK;
}
} break;
case CMD_9F_DATA_BUF_WITHOUT_BACK:
{
cmd_data_group_struct.cmd_buf[cmd_data_cnt] = val;
cmd_data_cnt++;
if(cmd_data_cnt >= g_pkg_dat_len)
{
cmd_data_cnt = 0;
cmd_data_9f_step = CMD_9F_DATA_CHACK_WITHOUT_BACK;
}
} break;
case CMD_9F_PRE_CHACK:
{
if(val == 0xA7)
{
cmd_data_9f_step = CMD_9F_DATA_IDLE;
back_9F_pre_ok();
}
} break;
case CMD_9F_ADDR_CHACK:
{
checksum = 0;
checksum = (uint8_t)(g_sub_amount_current) + (uint8_t)(g_sub_amount_current>>8) + (g_pkg_dat_len + 1) + g_pkg_cmd;
for(index = 0; index < 4; index++)
{
checksum += cmd_data_group_struct.cmd_addr[index];
}
checksum %= 0x100;
//printf("Get_cksum:%02X, val:%02X\n", checksum, val);
if(checksum == val)
{
cmd_data_9f_step = CMD_9F_ADDR_DONE;
}
else
{
cmd_data_9f_step = CMD_9F_ADDR_ERR;
}
} break;
case CMD_9F_DATA_CHACK:
{
checksum = 0;
checksum = (uint8_t)(g_sub_amount_current) + (uint8_t)(g_sub_amount_current>>8) + (g_pkg_dat_len + 1) + g_pkg_cmd;
for(index = 0; index < g_pkg_dat_len; index++)
{
checksum += cmd_data_group_struct.cmd_buf[index];
}
checksum %= 0x100;
if(checksum == val)
{
cmd_data_9f_step = CMD_9F_DATA_DONE;
}
else
{
cmd_data_9f_step = CMD_9F_DATA_ERR;
}
} break;
case CMD_9F_DATA_CHACK_WITHOUT_BACK:
{
checksum = 0;
checksum = (uint8_t)(g_sub_amount_current) + (uint8_t)(g_sub_amount_current>>8) + (g_pkg_dat_len + 1) + g_pkg_cmd;
for(index = 0; index < g_pkg_dat_len; index++)
{
checksum += cmd_data_group_struct.cmd_buf[index];
}
checksum %= 0x100;
if(checksum == val)
{
cmd_data_9f_step = CMD_9F_DATA_DONE_WITHOUT_BACK;
}
else
{
cmd_data_9f_step = CMD_9F_DATA_ERR_WITHOUT_BACK;
}
}
}
}// end UPDATE_ING
else if(update_status == UPDATE_DONE)
{
}
}
void app_update_9f_handle(void)
{
uint32_t _index = 0;
uint32_t write_addr = 0;
static uint32_t _base_addr_app = 0;
static unsigned char return_write = 1;
uint8_t equip_data[22];
if(update_status == UPDATE_ING)
{
if(cmd_data_9f_step == CMD_9F_ADDR_DONE)
{
// get_data_from_usart_flag = 1;
//update_status = UPDATE_ING;
cmd_data_9f_step = CMD_9F_DATA_IDLE;
// printf("Back_addr_ok\n");
back_9F_addr_ok();
}
else if(cmd_data_9f_step == CMD_9F_ADDR_ERR)
{
cmd_data_9f_step = CMD_9F_DATA_IDLE;
back_9F_addr_err();
}
else if(cmd_data_9f_step == CMD_9F_DATA_DONE_WITHOUT_BACK)
{
if(_base_addr_app == 0)
{
_base_addr_app = (cmd_data_group_struct.cmd_addr[0] << 24) + (cmd_data_group_struct.cmd_addr[1] << 16) + (cmd_data_group_struct.cmd_addr[2] << 8) + cmd_data_group_struct.cmd_addr[3] ;
g_cmd_data_group_act.write_addr = _base_addr_app;// - APP_START_ADDR;// + UPGRADE_DAT_START_ADDR;
g_cmd_data_group_act.sector_num = 0;
g_cmd_data_group_act.offset = 0;
// printf("_app_addr:%02X %02X %02X %02X\n", cmd_data_group_struct.cmd_addr[0], cmd_data_group_struct.cmd_addr[1], cmd_data_group_struct.cmd_addr[2], cmd_data_group_struct.cmd_addr[3]);
}
if(g_cmd_data_group_act.offset + g_pkg_dat_len >= 0x800)
{
_index = g_cmd_data_group_act.offset + g_pkg_dat_len - 0x800;
memcpy(&g_cmd_data_group_act.cmd_buf[g_cmd_data_group_act.offset], cmd_data_group_struct.cmd_buf, (0x800 - g_cmd_data_group_act.offset));
if((g_cmd_data_group_act.write_addr >= UPGRADE_DAT_START_ADDR) && (g_cmd_data_group_act.write_addr < (FLASH_BASE + 1024 * FLASH_SIZE)))
{
g_cmd_data_group_act.sector_num++;
flash_2kb_write(g_cmd_data_group_act.write_addr, g_cmd_data_group_act.cmd_buf);
// printf("Write_sector_num:%d, addr: 0x%08X\n", g_cmd_data_group_act.sector_num, g_cmd_data_group_act.write_addr);
g_cmd_data_group_act.write_addr += 0x800; // next sector
g_cmd_data_group_act.offset = 0;
}
else
{
back_9F_data_cmd(IAP_CMD_TRAN_PKG_WITHOUT_OKBACK, g_sub_amount_current,CMD_STATUS_9F_Err);
}
if(_index)
{
memcpy(g_cmd_data_group_act.cmd_buf, &cmd_data_group_struct.cmd_buf[g_pkg_dat_len - _index], _index);
g_cmd_data_group_act.offset += _index;
}
}
else
{
memcpy(&g_cmd_data_group_act.cmd_buf[g_cmd_data_group_act.offset], cmd_data_group_struct.cmd_buf, g_pkg_dat_len);
g_cmd_data_group_act.offset += g_pkg_dat_len;
}
if(g_sub_amount_current == 1)
{ // the end pkg
flash_write_by_sea_and_len(g_cmd_data_group_act.write_addr, g_cmd_data_group_act.cmd_buf, g_cmd_data_group_act.offset);
// set end pkg
update_status = UPDATE_DONE;
}
cmd_data_9f_step = CMD_9F_DATA_IDLE;
}
else if(cmd_data_9f_step == CMD_9F_DATA_ERR_WITHOUT_BACK)
{
cmd_data_9f_step = CMD_9F_DATA_IDLE;
back_9F_data_cmd(IAP_CMD_TRAN_PKG_WITHOUT_OKBACK, g_sub_amount_current,CMD_STATUS_9F_Err);
}
else if(cmd_data_9f_step == CMD_9F_DATA_DONE)
{
if(_base_addr_app == 0)
{
_base_addr_app = (cmd_data_group_struct.cmd_addr[0] << 24) + (cmd_data_group_struct.cmd_addr[1] << 16) + (cmd_data_group_struct.cmd_addr[2] << 8) + cmd_data_group_struct.cmd_addr[3] ;
g_cmd_data_group_act.write_addr = _base_addr_app;// - APP_START_ADDR; // + UPGRADE_DAT_START_ADDR;
g_cmd_data_group_act.sector_num = 0;
g_cmd_data_group_act.offset = 0;
// printf("_app_addr:%02X %02X %02X %02X\n", cmd_data_group_struct.cmd_addr[0], cmd_data_group_struct.cmd_addr[1], cmd_data_group_struct.cmd_addr[2], cmd_data_group_struct.cmd_addr[3]);
}
if(g_cmd_data_group_act.offset + g_pkg_dat_len >= 0x800)
{
_index = g_cmd_data_group_act.offset + g_pkg_dat_len - 0x800;
memcpy(&g_cmd_data_group_act.cmd_buf[g_cmd_data_group_act.offset], cmd_data_group_struct.cmd_buf, (0x800 - g_cmd_data_group_act.offset));
if((g_cmd_data_group_act.write_addr >= UPGRADE_DAT_START_ADDR) && (g_cmd_data_group_act.write_addr < (FLASH_BASE + 1024 * FLASH_SIZE)))
{
g_cmd_data_group_act.sector_num++;
flash_2kb_write(g_cmd_data_group_act.write_addr, g_cmd_data_group_act.cmd_buf);
// printf("Write_sector_num:%d, addr: 0x%08X\n", g_cmd_data_group_act.sector_num, g_cmd_data_group_act.write_addr);
g_cmd_data_group_act.write_addr += 0x800; // next sector
g_cmd_data_group_act.offset = 0;
}
else
{
// back_9F_data(g_sub_amount_current, CMD_STATUS_9F_Err);
back_9F_data(g_sub_amount_current, 0x02);
}
if(_index)
{
memcpy(g_cmd_data_group_act.cmd_buf, &cmd_data_group_struct.cmd_buf[g_pkg_dat_len - _index], _index);
g_cmd_data_group_act.offset += _index;
}
}
else
{
memcpy(&g_cmd_data_group_act.cmd_buf[g_cmd_data_group_act.offset], cmd_data_group_struct.cmd_buf, g_pkg_dat_len);
g_cmd_data_group_act.offset += g_pkg_dat_len;
}
if(g_sub_amount_current == 1)
{ // the end pkg
flash_write_by_sea_and_len(g_cmd_data_group_act.write_addr, g_cmd_data_group_act.cmd_buf, g_cmd_data_group_act.offset);
// set end pkg
update_status = UPDATE_DONE;
}
//printf("Rcv_sub_amount:%d\n", g_sub_amount_current);
cmd_data_9f_step = CMD_9F_DATA_IDLE;
back_9F_data(g_sub_amount_current, CMD_STATUS_9F_OK);
}
else if(cmd_data_9f_step == CMD_9F_DATA_ERR)
{
cmd_data_9f_step = CMD_9F_DATA_IDLE;
// back_9F_data(g_sub_amount_current, CMD_STATUS_9F_Err);
back_9F_data(g_sub_amount_current, 0x01);
}
}// end update_status == UPDATE_ING
else if(update_status == UPDATE_DONE)
{
{
// //write to the app
// g_cmd_data_group_act.sector_num++;
flash_unlock();
flash_sector_erase(IAP_UPGRADE_FLAG_ADDR);
flash_lock();
// write_addr = UPGRADE_DAT_START_ADDR;
// for(_index = 0; _index < g_cmd_data_group_act.sector_num; _index++)
// {
// flash_2kb_write_by_addr(_base_addr_app, write_addr);
// _base_addr_app += 0x800; //2K
// write_addr += 0x800;
// }
// crm_reset();
// /* jump and run in app */
// app_load(APP_START_ADDR);
delay_ms(10);
nvic_system_reset(); // reset mcu
}
}// end if UPDATE_DONE
else if(update_status == DGCMD_ING)
{
if(cmd_data_7f_step == CMD_7F_DATA_DONE)
{
switch(g_uart_buf_7f.cmd)
{
case GET_RADAR_EQUIPMENT:
{
get_cpu_id();
memcpy(equip_data, g_device_id, 6);
memcpy(&equip_data[6], Device_Name, sizeof(Device_Name));
_index = 6 + sizeof(Device_Name);
equip_data[_index++] = SOFTWARE_H;
equip_data[_index++] = SOFTWARE_L;
equip_data[_index++] = HARDWARE_H;
equip_data[_index++] = HARDWARE_L;
Com_Return_rader_para(usart_packet_processing(g_uart_buf_7f.cmd, &equip_data, _index));
delay_ms(100);
Com_Return_rader_para(usart_packet_processing(ENABLE_BLUETOOTH, &RS485_ID, 0));
//printf("send_dev_info_to_bt\r\n");
} break;
case BLUETOOTH_CONNECTION_STATUS:
{
if(g_uart_buf_7f.buf[0] == 0)
{
g_key_press_enable_ble = 0;
}
else if(g_uart_buf_7f.buf[0] == 1)
{
g_key_press_enable_ble = 1;
}
Com_Return_rader_para(usart_packet_processing(BLUETOOTH_CONNECTION_STATUS,&RS485_ID,0));
delay_ms(10);
Com_Return_rader_para(usart_packet_processing(ENABLE_BLUETOOTH, &RS485_ID, 0));
// printf("get_bt_enable_state:%d\r\n", g_key_press_enable_ble);
} break;
case RESET_RADAR_LOOP:
{
Com_Return_rader_para(usart_packet_processing(RESET_RADAR_LOOP_RETURN,&return_write,1));
delay_ms(10);
// printf("Rev_Reset_Cmd\r\n");
Com_Return_rader_para(usart_packet_processing(BLUETOOTH_CONNECTION_STATUS, &RS485_ID, 0));
//__set_FAULTMASK(1);
NVIC_SystemReset();
} break;
}
cmd_data_7f_step = CMD_7F_DATA_IDLE;
update_status = DGCMD_DONE;
}
else if(cmd_data_7f_step == CMD_7F_DATA_ERR)
{
cmd_data_7f_step = CMD_7F_DATA_IDLE;
update_status = DGCMD_DONE;
}
}
else if(update_status == DGCMD_DONE)
{
update_status = UPDATE_PRE;
}
}
/**
* @brief command response ok.
* @param none
* @retval none
*/
void back_ok(void)
{
usart_data_transmit(USART1, 0xCC);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xDD);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
/**
* @brief command response error.
* @param none
* @retval none
*/
void back_err(void)
{
usart_data_transmit(USART1, 0xEE);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
usart_data_transmit(USART1, 0xFF);
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
/* reset state machine of udgrade flow */
cmd_data_step = CMD_DATA_IDLE;
cmd_ctr_step = CMD_CTR_IDLE;
update_status = UPDATE_PRE;
cmd_addr_cnt = 0;
cmd_data_cnt = 0;
time_ira_cnt = 0;
get_data_from_usart_flag = 0;
}
/**
* @brief iap upgrade app handle.
* @param none
* @retval none
*/
void iap_upgrade_app_handle(void)
{
// command_handle();
// app_update_handle();
}
void iap_upgrade_app_9F_handle(void)
{
command_9f_handle();
app_update_9f_handle();
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/main.c
+87
View File
@@ -0,0 +1,87 @@
/**
**************************************************************************
* @file main.c
* @brief main program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_board.h"
#include "at32f421_clock.h"
#include "tmr.h"
#include "usart.h"
#include "flash.h"
#include "iap.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
/**
* @brief main function.
* @param none
* @retval none
*/
int main(void)
{
system_clock_config();
at32_board_init();
/* config nvic priority group */
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
/* check iap_upgrade_flag flag */
if(flash_upgrade_flag_read() == RESET)
{
/* check app starting address whether 0x08xxxxxx */
if(((*(uint32_t*)(APP_START_ADDR + 4)) & 0xFF000000) == 0x08000000)
app_load(APP_START_ADDR);
}
/* init usart used for app update */
// uart_init(115200);
uart_init(192000);
/* check whether need to upgrade, if yes, response ok to pc-tool */
if(flash_upgrade_flag_read() != RESET)
{
back_9F_pre_ok();
}
/* init tmr used for show code running state(led cycle toggle) */
tmr_init();
while(1)
{
/* upgrade handle */
iap_upgrade_app_9F_handle();
}
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/tmr.c
+97
View File
@@ -0,0 +1,97 @@
/**
**************************************************************************
* @file tmr.c
* @brief tmr program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "at32f421_board.h"
#include "tmr.h"
#include "iap.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
uint8_t time_ira_cnt=0;
uint8_t get_data_from_usart_flag = 0; /* flag for timer out in upgrade flow */
/**
* @brief init tmr.
* @param none
* @retval none
*/
void tmr_init(void)
{
crm_clocks_freq_type crm_clocks_freq_struct = {0};
crm_periph_clock_enable(CRM_TMR3_PERIPH_CLOCK, TRUE);
/* enable the tmr3 global interrupt */
nvic_irq_enable(TMR3_GLOBAL_IRQn, 1, 0);
/* get system clock */
crm_clocks_freq_get(&crm_clocks_freq_struct);
/* time base configuration */
tmr_base_init(TMR3, 10000, crm_clocks_freq_struct.ahb_freq / 10000);
tmr_cnt_dir_set(TMR3, TMR_COUNT_UP);
/* overflow interrupt enable */
tmr_interrupt_enable(TMR3, TMR_OVF_INT, TRUE);
/* enable tmr */
tmr_counter_enable(TMR3, TRUE);
}
/**
* @brief tmr3 global interrupt handler.
* @param none
* @retval none
*/
void TMR3_GLOBAL_IRQHandler(void)
{
if(tmr_interrupt_flag_get(TMR3, TMR_OVF_FLAG) == SET)
{
tmr_flag_clear(TMR3, TMR_OVF_FLAG);
at32_led_toggle(LED2);
if(get_data_from_usart_flag)
{
if((++time_ira_cnt) == 0x00)
time_ira_cnt = 0xFF;
if(time_ira_cnt > 2)
back_err();
if(time_ira_cnt > 5)
crm_periph_clock_enable(LED2_GPIO_CRM_CLK, FALSE);
}
}
}
/**
* @}
*/
/**
* @}
*/
DLD960LoopBootloader/utilities/at32f421_usart_iap_demo/source_code/bootloader/src/usart.c
+206
View File
@@ -0,0 +1,206 @@
/**
**************************************************************************
* @file usart.c
* @brief usart program
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include <string.h>
#include "usart.h"
#include "tmr.h"
/** @addtogroup UTILITIES_examples
* @{
*/
/** @addtogroup USART_iap_bootloader
* @{
*/
usart_group_type usart_group_struct;
cpu_t stm32cpu;
uint8_t g_device_id[6] = "";
void get_cpu_id(void)
{
uint8_t i = 0;
uint8_t check_xor = 0x21;
uint8_t check_sum = 0x21;
memcpy(&stm32cpu, CPU_ID_BASE_ADDR, sizeof(cpu_t));
memcpy(g_device_id, CPU_ID_BASE_ADDR, 4);
for(; i<12; i++)
{
check_xor ^= stm32cpu.info.byte[i];
check_sum += stm32cpu.info.byte[i]; // TODO: Ӧ¸øĎª +
}
g_device_id[4] = check_xor;
g_device_id[5] = check_sum % 0x100;
}
/*******************************************************************************
* : usart1_packet_processing
* 说明 : 将数据包处理为串口发送的协议
*******************************************************************************/
comStruct usart_packet_processing(uint8_t cmd, void *buff, uint8_t LEN)
{
comStruct data;
uint8_t i;
data.head = 0X7F;
data.addr = 0x80;
data.len = LEN+1;
data.cmd = cmd;
data.xor = data.addr ^ data.len ^ data.cmd;
data.sum = data.addr + data.len + data.cmd;
if(LEN)
{
memcpy(&data.dat,buff, LEN);
}
for(i = 0; i < LEN; i++)
{
data.xor ^= data.dat[i];
data.sum += data.dat[i];
}
data.sum %= 0x100;
data.dat[LEN] = data.xor;
data.dat[LEN + 1] = data.sum;
return data;
}
/*******************************************************************************
* 函数名称 : Com_Return_rader_para
* 说明 : 将数据包处理为串口发送的协议
*******************************************************************************/
void Com_Return_rader_para(comStruct para)
{
unsigned char *ptr;
unsigned char i;
ptr = &para.head;
uart1_send_buf(ptr, para.len + 5);
}
/**
* @brief init usart.
* @param none
* @retval none
*/
void uart_init(uint32_t baudrate)
{
gpio_init_type gpio_init_struct;
/* enable the usart and it's io clock */
crm_periph_clock_enable(CRM_USART1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
/* set default parameter */
gpio_default_para_init(&gpio_init_struct);
/* configure the usart1_tx/rx pa9/pa10 */
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = GPIO_PINS_9 | GPIO_PINS_10;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(GPIOA, &gpio_init_struct);
/* config usart1 iomux */
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE9, GPIO_MUX_1);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE10, GPIO_MUX_1);
/*configure usart nvic interrupt */
nvic_irq_enable(USART1_IRQn, 0, 0);
/*configure usart param*/
usart_init(USART1, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART1, TRUE);
usart_receiver_enable(USART1, TRUE);
usart_interrupt_enable(USART1, USART_RDBF_INT, TRUE);
usart_enable(USART1, TRUE);
}
void usart1_sendstring(uint8_t *buf, uint16_t len)
{
uint16_t _len = len;
while(_len){
while(usart_flag_get(USART1, USART_TDBE_FLAG) == RESET);
usart_data_transmit(USART1, *buf++);
_len--;
}
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
void uart1_send_buf(uint8_t *buf, uint8_t len)
{
uint16_t _len = len;
while(_len){
while(usart_flag_get(USART1, USART_TDBE_FLAG) == RESET);
usart_data_transmit(USART1, *buf++);
_len--;
}
while(usart_flag_get(USART1, USART_TDC_FLAG) == RESET);
}
/**
* @brief usart1 interrupt handler.
* @param none
* @retval none
*/
void USART1_IRQHandler(void)
{
uint16_t reval;
time_ira_cnt = 0; /* clear upgrade time out flag */
if(usart_interrupt_flag_get(USART1, USART_RDBF_FLAG) != RESET)
{
reval = usart_data_receive(USART1);
if(usart_group_struct.count > (USART_REC_LEN - 1))
{
usart_group_struct.count = 0;
usart_group_struct.head = 0;
usart_group_struct.tail = 0;
}
else
{
usart_group_struct.count++;
usart_group_struct.buf[usart_group_struct.head++] = reval;
if(usart_group_struct.head > (USART_REC_LEN - 1))
{
usart_group_struct.head = 0;
}
}
}
}
/**
* @}
*/
/**
* @}
*/
vd960Loop/docs/devlog.md
+39
View File
@@ -4,6 +4,45 @@
---
## 2026-08-28 — 看门狗升级：双保险喂狗模式 + 超时对齐 V4B（1.64s）
### 背景
与 DLD154V4B（同款 AT32F421）看门狗实现对照后发现三个问题：
| 问题 | 说明 |
|------|------|
| **直喂模式缺 ISR 活性检测** | 原实现主循环每 10ms 无条件 `wdt_feed()`——TMR15 ISR 死掉但主循环活着时，看门狗照样被喂，系统"假活"（时序状态机全停但永不复位） |
| **超时 3s 偏长** | `div=64, rld=1875` → 3s；V4B 已用 1.64s，复位自愈更快 |
| **注释矛盾** | `main.c` 注释写"重载值=4687 超时≈3秒"（4687 是 7.5s 的算法），实际 1875→3s |
### 改动（对齐 DLD154V4B V2.10）
```c
// TaskLoop.h
#define WDT_COUNTER_LIMIT 100 // 喂狗周期 500ms (TMR15 5ms × 100)
#define WDT_DIV 2 // IWDT 分频枚举值: 2 = WDT_CLK_DIV_16 (实际分频 16)
#define WDT_RLD 4095 // 12bit 重装载 → 超时 ≈ 1.64s
```
| 文件 | 变更 |
|------|------|
| `src/main.c` | `wdt_init()`：`WDT_CLK_DIV_64/1875` → `WDT_CLK_DIV_16/4095`（超时 3s→1.64s）；`wdt_feed` 定义删除（移至 TaskLoop.c）；注释修正 |
| `src/TaskLoop.c` | +`g_wdg_counter` + `poll_wdg()`（500ms 才 reload）；TMR15 ISR 5ms 递增；调用点 `wdt_feed()`→`poll_wdg()` |
| `inc/TaskLoop.h` | +WDT 宏 + `poll_wdg` 声明 + `g_wdg_counter` extern（删 `wdt_feed`） |
### 验证
- 隔离测试（host gcc mock 3bit 寄存器语义）3 项断言全过：分频 16/重载 4095/超时 1638ms > 500ms 喂狗周期、10s 喂狗 20 次（500ms 精确）、ISR 死不喂狗
- 双保险语义：ISR 死 → 计数不涨 → 永不喂狗；主循环死 → poll_wdg 不执行 → 超时复位
- 待现场验证：LSI 实际频率偏差对复位时间的影响
### ⚠ 踩坑提醒（V4B 同源事故）
`wdt_divider_set()` 参数是**枚举值**不是分频数值（`WDT_CLK_DIV_16=0x02`，寄存器只取低 3 位）——V4B 曾把 `WDT_DIV=16` 当数值传入 → 实际分频 4 → 超时 410ms < 500ms 喂狗周期 → **不断复位重启**。本次 vd960Loop 直接沿用枚举写法，避免同坑。
---
## 2026-08-27 — LOOP_MEASURE_BASE 归一化基数上报（协议 V1.09）
### 背景
vd960Loop/utilities/at32f421_freertos_demo/inc/TaskLoop.h
+11 -1
View File
@@ -41,6 +41,15 @@
#define FREEZE_TIMEOUT 1000 // 冻结超时: ~10s @ 10ms/tick
#define FREEZE_STABILITY_RATE 2 // 稳定性窗口: 参考值的 ±2%
/*===========================================================================
* 看门狗 (IWDT) - 对齐 DLD154V4B V2.10
* 双保险模式: TMR15 ISR 5ms 递增 g_wdg_counter, 主循环 poll_wdg() 每 500ms 喂狗
* 超时 = WDT_DIV 枚举分频 x (WDT_RLD+1) / LSI(约40kHz) 约 1.64s
*===========================================================================*/
#define WDT_COUNTER_LIMIT 100 // 喂狗周期 500ms (TMR15 5ms x 100)
#define WDT_DIV 2 // IWDT 分频枚举值: 2 = WDT_CLK_DIV_16 (实际分频 16; 勿传 16!)
#define WDT_RLD 4095 // 12bit 重装载 -> 超时约 1.64s
/*===========================================================================
* 离开检测: 1 = 平坦性三条件 (CN200910309382), 0 = cnt_release 防抖
*===========================================================================*/
@@ -228,7 +237,8 @@ uint8_t update_moving_average(uint32_t* p_sum, uint16_t* p_cnt,
void set_loops_relay_on(uint8_t loop_num);
void set_loops_relay_off(uint8_t loop_num);
void wdt_feed(void);
void poll_wdg(void);
extern volatile uint16_t g_wdg_counter; // 看门狗活性计数 (TMR15 5ms 递增)
extern TaskHandle_t usart_task_handler;
vd960Loop/utilities/at32f421_freertos_demo/src/TaskLoop.c
+19 -1
View File
@@ -24,6 +24,7 @@ Loop154_States g_loop_states = {0};
uint32_t g_sys_freq = 0;
uint8_t g_input_div = 1;
uint32_t g_safe_max_cnt = LC_HOLD_TIME;
volatile uint16_t g_wdg_counter = 0; // 看门狗活性计数 (TMR15 ISR 5ms 递增)
/*===========================================================================
* 一阶 IIR 低通滤波器（对齐 DLD154V4B）
@@ -252,6 +253,9 @@ void TMR15_GLOBAL_IRQHandler(void)
if (tmr_interrupt_flag_get(TMR15, TMR_OVF_FLAG) != RESET) {
/*--- 看门狗活性计数 (5ms) ---*/
g_wdg_counter++;
/*--- 50ms tick 分频 ---*/
TM1cnt++;
if (TM1cnt >= 10) {
@@ -657,6 +661,20 @@ void vd1_task_per_channel(Loop154_Unit *unit)
/*===========================================================================
* loop_task_function — FreeRTOS 主任务（对齐 DLD154V4B main 循环）
/*===========================================================================
* 看门狗喂狗 (双保险, 对齐 DLD154V4B V2.10)
* TMR15 ISR 5ms 递增 g_wdg_counter; 计数达 100 (500ms) 才 reload
* ISR 死 -> 计数不涨 -> 永不喂狗; 主循环死 -> 本函数不执行 -> 超时复位
*===========================================================================*/
void poll_wdg(void)
{
if (g_wdg_counter >= WDT_COUNTER_LIMIT) { // 100 x 5ms = 500ms
g_wdg_counter = 0;
wdt_counter_reload();
}
}
/*===========================================================================
* 10ms 周期，独立处理每路线圈。
*===========================================================================*/
void loop_task_function(void *pvParameters)
@@ -705,7 +723,7 @@ void loop_task_function(void *pvParameters)
}
}
wdt_feed();
poll_wdg();
vTaskDelay(10); // 10ms tick, M4 优化: 双路 IIR + 进入确认 + 斜率限幅
}
}
vd960Loop/utilities/at32f421_freertos_demo/src/main.c
+7 -18
View File
@@ -59,9 +59,8 @@ __IO uint32_t TimingDelayDec;
TaskHandle_t loop_task_handler;
// 看门狗相关
#define WDT_TIMEOUT_MS 3000 // 看门狗超时时间 3秒
#define WDT_TIMEOUT_MS 1600 // 看门狗超时时间: IWDT div16 rld4095, LSI约40kHz -> ~1.64s
void wdt_init(void);
void wdt_feed(void);
tmr_output_config_type tmr_oc_init_structure;
@@ -104,20 +103,19 @@ void InitPkgUart(Pkg_Uart * pkg){
* @param none
* @retval none
* @note 超时时间 = (预分频系数 × 重载值) / LSI频率
* LSI频率约 40kHz，预分频64，重载值=4687，超时≈ 3秒
* LSI频率约 40kHz，预分频16（枚举 WDT_CLK_DIV_16），重载值=4095，超时≈ 1.64秒
*/
void wdt_init(void)
{
// 使能看门狗寄存器写访问
wdt_register_write_enable(TRUE);
// 设置预分频系数为 64
wdt_divider_set(WDT_CLK_DIV_64);
// 设置预分频: 必须用枚举 WDT_CLK_DIV_16 (=0x02), 勿传数值 16! (V4B 踩坑)
wdt_divider_set(WDT_CLK_DIV_16);
// 设置重载值
// 超时时间 = (64 × 4687) / 40000 ≈ 7.5秒
// 如果需要 3秒: (64 × 1875) / 40000 = 3秒
wdt_reload_value_set(1875);
// 设置重载值 4095 (12bit 最大)
// 超时时间 = (16 × 4096) / 40000 ≈ 1.64秒
wdt_reload_value_set(4095);
// 重载计数器
wdt_counter_reload();
@@ -128,15 +126,6 @@ void wdt_init(void)
PRINT("Watchdog initialized, timeout: %d ms\n", WDT_TIMEOUT_MS);
}
/**
* @brief 喂狗（重载看门狗计数器）
* @param none
* @retval none
*/
void wdt_feed(void)
{
wdt_counter_reload();
}
uint16_t timer_period = 0;
uint16_t channel1_pulse = 0;