feat(vd960Loop): 看门狗升级双保险喂狗模式 + 超时对齐 V4B（1.64s）
对照 DLD154V4B V2.10（同款 AT32F421）: - 原直喂模式缺 ISR 活性检测: TMR15 ISR 死但主循环活 -> 看门狗永不复位(假活) - 升级: TMR15 ISR 5ms 递增 g_wdg_counter + 主循环 poll_wdg() 500ms 才 reload - 超时 3s(div64/rld1875) -> 1.64s(div16枚举/rld4095) - wdt_feed 定义移至 TaskLoop.c 改名 poll_wdg, 与 V4B 同构 - 修正 main.c 注释矛盾(4687 vs 1875); 沿用 WDT_CLK_DIV_16 枚举写法避免 V4B 同源传值 bug - 隔离测试 3 项断言全过(分频16/超时1638ms>500ms/10s喂20次/ISR死不喂)
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wangfq
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/**
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**************************************************************************
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* @file at32f421_debug.h
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* @brief at32f421 debug header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F421_DEBUG_H
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#define __AT32F421_DEBUG_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f421.h"
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/** @addtogroup AT32F421_periph_driver
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* @{
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*/
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/** @addtogroup DEBUG
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* @{
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*/
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/** @defgroup DEBUG_mode_definition
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* @{
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*/
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#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
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#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
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#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
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#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
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#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
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#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
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#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
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#define DEBUG_ERTC_PAUSE 0x00004000 /*!< debug ertc pause */
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#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
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#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
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#define DEBUG_TMR6_PAUSE 0x00080000 /*!< debug timer6 pause */
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#define DEBUG_ERTC_512_PAUSE 0x00200000 /*!< debug ertc 512 pause */
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#define DEBUG_TMR15_PAUSE 0x00400000 /*!< debug timer15 pause */
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#define DEBUG_TMR16_PAUSE 0x00800000 /*!< debug timer16 pause */
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#define DEBUG_TMR17_PAUSE 0x01000000 /*!< debug timer17 pause */
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#define DEBUG_TMR14_PAUSE 0x08000000 /*!< debug timer14 pause */
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/**
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* @}
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*/
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/** @defgroup DEBUG_exported_types
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* @{
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*/
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/**
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* @brief type define debug register all
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*/
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typedef struct
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{
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/**
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* @brief debug idcode register, offset:0x00
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*/
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union
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{
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__IO uint32_t pid;
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struct
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{
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__IO uint32_t pid : 32;/* [31:0] */
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} idcode_bit;
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};
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/**
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* @brief debug ctrl register, offset:0x04
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*/
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union
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{
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__IO uint32_t ctrl;
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struct
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{
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__IO uint32_t sleep_debug : 1;/* [0] */
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__IO uint32_t deepsleep_debug : 1;/* [1] */
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__IO uint32_t standby_debug : 1;/* [2] */
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__IO uint32_t reserved1 : 5;/* [7:3] */
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__IO uint32_t wdt_pause : 1;/* [8] */
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__IO uint32_t wwdt_pause : 1;/* [9] */
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__IO uint32_t tmr1_pause : 1;/* [10] */
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__IO uint32_t reserved2 : 1;/* [11] */
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__IO uint32_t tmr3_pause : 1;/* [12] */
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__IO uint32_t reserved3 : 1;/* [13] */
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__IO uint32_t ertc_pause : 1;/* [14] */
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__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
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__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
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__IO uint32_t reserved4 : 2;/* [18:17] */
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__IO uint32_t tmr6_pause : 1;/* [19] */
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__IO uint32_t reserved5 : 1;/* [20] */
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__IO uint32_t ertc_512_pause : 1;/* [21] */
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__IO uint32_t tmr15_pause : 1;/* [22] */
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__IO uint32_t tmr16_pause : 1;/* [23] */
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__IO uint32_t tmr17_pause : 1;/* [24] */
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__IO uint32_t reserved6 : 2;/* [26:25] */
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__IO uint32_t tmr14_pause : 1;/* [27] */
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__IO uint32_t reserved7 : 4;/* [31:28] */
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} ctrl_bit;
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};
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} debug_type;
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/**
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* @}
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*/
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#define DEBUGMCU ((debug_type *) DEBUG_BASE)
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/** @defgroup DEBUG_exported_functions
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* @{
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*/
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uint16_t debug_device_id_get(void);
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void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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