wangfq
95808f9f25
- 用 DLD154V4B vd1_task/per_channel 替换 vds_task 复杂算法
- 移除 FUNCTION_B/二次判断/快速变化/多重确认等增强特性
- 保留平坦性离开算法 (CN200910309382)，每通道独立状态
- 灵敏度表改为 DLD154V4B 4级: {216,108,36,10} / {108,72,18,9}
- 清理废弃类型: FltHistoryManager, Loop_ACS_Info, StageRangeConfig 等
- 首次添加 vd960DBN 完整源码
286 lines
8.8 KiB
C
286 lines
8.8 KiB
C
/**
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**************************************************************************
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* @file at32f421_dma.c
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* @brief contains all the functions for the dma firmware library
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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#include "at32f421_conf.h"
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/** @addtogroup AT32F421_periph_driver
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* @{
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*/
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/** @defgroup DMA
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* @brief DMA driver modules
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* @{
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*/
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#ifdef DMA_MODULE_ENABLED
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/** @defgroup DMA_private_functions
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* @{
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*/
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/**
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* @brief reset the dmax channely registers.
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @retval none
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*/
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void dma_reset(dma_channel_type* dmax_channely)
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{
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uint32_t temp = 0;
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dmax_channely->ctrl_bit.chen = FALSE;
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dmax_channely->ctrl = 0;
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dmax_channely->dtcnt = 0;
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dmax_channely->paddr = 0;
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dmax_channely->maddr = 0;
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temp = (uint32_t)dmax_channely;
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/* dma1 channel */
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DMA1->clr |= (uint32_t)(0x0f << ((((temp & 0xff) - 0x08) / 0x14) * 4));
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}
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/**
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* @brief set the number of data to be transferred
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @param data_number: the number of data to be transferred(0x0000~0xFFFF)
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* transfer.
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* @retval none.
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*/
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void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number)
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{
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dmax_channely->dtcnt = data_number;
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}
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/**
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* @brief get number of data from dtcnt register
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @retval the number of data.
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*/
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uint16_t dma_data_number_get(dma_channel_type* dmax_channely)
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{
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return (uint16_t)dmax_channely->dtcnt;
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}
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/**
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* @brief enable or disable dma interrupt
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @param dma_int:
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* this parameter can be any combination of the following values:
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* - DMA_FDT_INT
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* - DMA_HDT_INT
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* - DMA_DTERR_INT
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* @param new_state (TRUE or FALSE)
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* @retval none
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*/
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void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state)
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{
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if (new_state != FALSE)
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{
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dmax_channely->ctrl |= dma_int;
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}
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else
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{
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dmax_channely->ctrl &= ~dma_int;
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}
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}
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/**
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* @brief enable or disable dma channely
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @param new_state (TRUE or FALSE)
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* @retval None
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*/
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void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state)
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{
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dmax_channely->ctrl_bit.chen = new_state;
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}
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/**
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* @brief get dma interrupt flag
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* @param dmax_flag
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* this parameter can be one of the following values:
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* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
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* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
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* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
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* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
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* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
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* @retval state of dma flag
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*/
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flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
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{
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flag_status status = RESET;
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uint32_t temp = 0;
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temp = DMA1->sts;
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if ((temp & dmax_flag) != (uint16_t)RESET)
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{
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status = SET;
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}
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else
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{
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status = RESET;
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}
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return status;
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}
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/**
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* @brief get dma flag
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* @param dmax_flag
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* this parameter can be one of the following values:
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* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
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* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
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* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
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* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
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* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
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* @retval state of dma flag
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*/
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flag_status dma_flag_get(uint32_t dmax_flag)
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{
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flag_status status = RESET;
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uint32_t temp = 0;
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temp = DMA1->sts;
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if ((temp & dmax_flag) != (uint16_t)RESET)
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{
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status = SET;
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}
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else
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{
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status = RESET;
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}
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return status;
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}
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/**
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* @brief clear dma flag
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* @param dmax_flag
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* this parameter can be one of the following values:
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* - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
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* - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
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* - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
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* - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
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* - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
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* @retval none
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*/
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void dma_flag_clear(uint32_t dmax_flag)
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{
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DMA1->clr = dmax_flag;
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}
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/**
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* @brief dma init config with its default value.
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* @param dma_init_struct : pointer to a dma_init_type structure which will
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* be initialized.
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* @retval none
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*/
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void dma_default_para_init(dma_init_type* dma_init_struct)
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{
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dma_init_struct->peripheral_base_addr = 0x0;
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dma_init_struct->memory_base_addr = 0x0;
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dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
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dma_init_struct->buffer_size = 0x0;
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dma_init_struct->peripheral_inc_enable = FALSE;
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dma_init_struct->memory_inc_enable = FALSE;
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dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
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dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
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dma_init_struct->loop_mode_enable = FALSE;
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dma_init_struct->priority = DMA_PRIORITY_LOW;
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}
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/**
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* @brief dma init
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* @param dmax_channely:
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* this parameter can be one of the following values:
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* - DMA1_CHANNEL1
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* - DMA1_CHANNEL2
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* - DMA1_CHANNEL3
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* - DMA1_CHANNEL4
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* - DMA1_CHANNEL5
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* @param dma_initstruct : pointer to a dma_init_type structure.
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* @retval none
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*/
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void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct)
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{
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/* clear ctrl register dtd bit and m2m bit */
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dmax_channely->ctrl &= 0xbfef;
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dmax_channely->ctrl |= dma_init_struct->direction;
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dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
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dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
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dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
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dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
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dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
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dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
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dmax_channely->dtcnt = dma_init_struct->buffer_size;
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dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
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dmax_channely->maddr = dma_init_struct->memory_base_addr;
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}
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/**
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* @}
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*/
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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